JAJSRL8 データシート

JAJSRL8I June 2007 – August 2024 CDCE913 , CDCEL913

PRODUCTION DATA

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
OVERALL PARAMETER
I_DD	Supply current (see Figure 5-1)	All outputs off, f_CLK = 27 MHz, f_VCO = 135 MHz; f_OUT = 27 MHz	All PLLS on		11		mA
I_DD	Supply current (see Figure 5-1)		Per PLL		9		mA
I_DD(OUT)	Supply current (see Figure 5-2 and Figure 5-3)	No load, all outputs on, f_OUT = 27 MHz	V_DDOUT = 3.3 V		1.3		mA
I_DD(OUT)	Supply current (see Figure 5-2 and Figure 5-3)	No load, all outputs on, f_OUT = 27 MHz	V_DDOUT = 1.8 V		0.7		mA
I_DD(PD)	Power-down current. Every circuit powered down except SDA/SCL	f_IN = 0 MHz, V_DD = 1.9 V			30		μA
V_(PUC)	Supply voltage V_dd threshold for power-up control circuit			0.85		1.45	V
f_VCO	VCO frequency range of PLL			80		230	MHz
f_OUT	LVCMOS output frequency	V_DDOUT = 3.3 V				230	MHz
f_OUT	LVCMOS output frequency	V_DDOUT = 1.8 V				230	MHz
LVCMOS PARAMETER
V_IK	LVCMOS input voltage	V_DD = 1.7 V; I_I = –18 mA				–1.2	V
I_I	LVCMOS input current	V_I = 0 V or V_DD; V_DD = 1.9 V				±5	μA
I_IH	LVCMOS input current for S0/S1/S2	V_I = V_DD; V_DD = 1.9 V				5	μA
I_IL	LVCMOS input current for S0/S1/S2	V_I = 0 V; V_DD = 1.9 V				–4	μA
C_I	Input capacitance at Xin/Clk	V_IClk = 0 V or V_DD			6		pF
	Input capacitance at Xout	V_IXout = 0 V or V_DD			2
	Input capacitance at S0/S1/S2	V_IS = 0 V or V_DD			3
CDCE913 - LVCMOS PARAMETER FOR V_DDOUT = 3.3 V – MODE
V_OH	LVCMOS high-level output voltage	V_DDOUT = 3 V, I_OH = –0.1 mA		2.9			V
		V_DDOUT = 3 V, I_OH = –8 mA		2.4
		V_DDOUT = 3 V, I_OH = –12 mA		2.2
V_OL	LVCMOS low-level output voltage	V_DDOUT = 3 V, I_OL = 0.1 mA				0.1	V
		V_DDOUT = 3 V, I_OL = 8 mA				0.5
		V_DDOUT = 3 V, I_OL = 12 mA				0.8
t_PLH, t_PHL	Propagation delay	PLL bypass			3.2		ns
t_r/t_f	Rise and fall time	V_DDOUT = 3.3 V (20%–80%)			0.6		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1 PLL switching, Y2-to-Y3			50	70	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1 PLL switching, Y2-to-Y3			60	100	ps
t_sk(o)	Output skew ⁽⁴⁾, See Table 7-2	f_OUT = 50 MHz; Y1-to-Y3				60	ps
odc	Output duty cycle ⁽⁵⁾	f_VCO = 100 MHz; Pdiv = 1		45%		55%
CDCE913 – LVCMOS PARAMETER for V_DDOUT = 2.5 V – MODE
V_OH	LVCMOS high-level output voltage	V_DDOUT = 2.3 V, I_OH = –0.1 mA		2.2			V
		V_DDOUT = 2.3 V, I_OH = –6 mA		1.7
		V_DDOUT = 2.3 V, I_OH = –10 mA		1.6
V_OL	LVCMOS low-level output voltage	V_DDOUT = 2.3 V, I_OL = 0.1 mA				0.1	V
		V_DDOUT = 2.3 V, I_OL = 6 mA				0.5
		V_DDOUT = 2.3 V, I_OL = 10 mA				0.7
t_PLH, t_PHL	Propagation delay	PLL bypass			3.6		ns
t_r/t_f	Rise and fall time	V_DDOUT = 2.5 V (20%–80%)			0.8		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1 PLL switching, Y2-to-Y3			50	70	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1 PLL switching, Y2-to-Y3			60	100	ps
t_sk(o)	Output skew⁽⁴⁾ , See Table 7-2	f_OUT = 50 MHz; Y1-to-Y3				60	ps
odc	Output duty cycle⁽⁵⁾	f_VCO = 100 MHz; Pdiv = 1		45%		55%
CDCEL913 — LVCMOS PARAMETER for V_DDOUT = 1.8 V – MODE
V_OH	LVCMOS high-level output voltage	V_DDOUT = 1.7 V, I_OH = –0.1 mA		1.6			V
		V_DDOUT = 1.7 V, I_OH = –4 mA		1.4
		V_DDOUT = 1.7 V, I_OH = –8 mA		1.1
V_OL	LVCMOS low-level output voltage	V_DDOUT = 1.7 V, I_OL = 0.1 mA				0.1	V
		V_DDOUT = 1.7 V, I_OL = 4 mA				0.3
		V_DDOUT = 1.7 V, I_OL = 8 mA				0.6
t_PLH, t_PHL	Propagation delay	PLL bypass			2.6		ns
t_r/t_f	Rise and fall time	V_DDOUT = 1.8 V (20%–80%)			0.7		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1 PLL switching, Y2-to-Y3			80	110	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1 PLL switching, Y2-to-Y3			100	130	ps
t_sk(o)	Output skew⁽⁴⁾, See Table 7-2	f_OUT = 50 MHz; Y1-to-Y3				50	ps
odc	Output duty cycle⁽⁵⁾	f_VCO = 100 MHz; Pdiv = 1		45%		55%
SDA/SCL PARAMETER
V_IK	SCL and SDA input clamp voltage	V_DD = 1.7 V; I_I = –18 mA				–1.2	V
I_IH	SCL and SDA input current	V_I = V_DD; V_DD = 1.9 V				±10	μA
V_IH	SDA/SCL input high voltage⁽⁶⁾			0.7 × V_DD			V
V_IL	SDA/SCL input low voltage⁽⁶⁾					0.3 × V_DD	V
V_OL	SDA low-level output voltage	I_OL = 3 mA, V_DD = 1.7 V				0.2 × V_DD	V
C_I	SCL/SDA input capacitance	V_I = 0 V or V_DD			3	10	pF

(1) All typical values are at respective nominal V_DD.

(2) 10,000 cycles.

(3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, f_VCO = 108 MHz, f_OUT = 27 MHz (measured at Y2).

(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.

(5) odc depends on output rise and fall time (t_r/t_f); data sampled on rising edge (t_r)

(6) SDA and SCL pins are 3.3-V tolerant.