JAJSRL8I June   2007  – August 2024 CDCE913 , CDCEL913

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL #GUID-DE171716-D3A0-4375-A25C-58C636304087/SCAS849414
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-up
        4. 8.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs/Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.3 Recommended Operating Conditions

MINNOMMAXUNIT
VDDDevice supply voltage1.71.81.9V
VOOutput Yx supply voltage for CDCE913, VDDOUT2.33.6V
Output Yx supply voltage for CDCEL913, VDDOUT1.71.9
VILLow-level input voltage, LVCMOS0.3 × VDDV
VIHHigh-level input voltage, LVCMOS0.7 × VDDV
VI (thresh)Input voltage threshold, LVCMOS0.5 × VDDV
VI(S)Input voltage range, S001.9V
Input voltage range S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD03.6
VI(CLK)Input voltage range CLK01.9V
IOH /IOLOutput current (VDDOUT = 3.3 V)±12mA
Output current (VDDOUT = 2.5 V)±10
Output current (VDDOUT = 1.8 V)±8
CLOutput load, LVCMOS15pF
TAOperating free-air temperature–4085°C
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS(1)
fXtalCrystal input frequency range (fundamental mode)82732MHz
ESREffective series resistance100Ω
fPRPulling range (0 V ≤ VCtrl ≤ 1.8 V)(2)±120±150ppm
Frequency control voltage, VCtrl0VDDV
C0/C1Pullability ratio220
CLOn-chip load capacitance at Xin and Xout020pF
(1) For more information about VCXO configuration, and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (application note).
(2) Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120 ppm applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (application note).