JAJSRL8I June   2007  – August 2024 CDCE913 , CDCEL913

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL #GUID-DE171716-D3A0-4375-A25C-58C636304087/SCAS849414
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-up
        4. 8.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs/Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.1 Control Terminal Configuration

The CDCE913 or CDCEL913 has three user-definable control terminals (S0, S1, and S2), which allow external control of device settings. The devices can be programmed to any of the following functions:

  • Spread-spectrum clocking selection → spread type and spread amount selection
  • Frequency selection → switching between any of two user-defined frequencies
  • Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 7-1 and Table 7-2 explain these settings.

Table 7-1 Control Terminal Definition
EXTERNAL CONTROL BITSPLL1 SETTINGY1 SETTING
Control functionPLL frequency selectionSSC selectionOutput Y2/Y3 selectionOutput Y1 and power-down selection
Table 7-2 PLLx Setting (Can Be Selected for Each PLL Individually)(1)
SSCx [3 Bits]CENTERDOWN
SSC SELECTION (CENTER/DOWN)
0000% (off)0% (off)
001±0.25%–0.25%
010±0.5%–0.5%
011±0.75%–0.75%
100±1.0%–1.0%
101±1.25%–1.25%
110±1.5%–1.5%
111±2.0%–2.0%
(1) Center-spread/down-spread, Frequency0/Frequency1 and State0/State1 are user-definable in PLLx configuration register.
Table 7-3 PLLx Setting, Frequency Selection (Can Be Selected for Each PLL Individually)(1)
FSxFUNCTION
0Frequency0
1Frequency1
(1) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
Table 7-4 PLLx Setting, Output Selection(1) (Y2 ... Y3)
YxYxFUNCTION
0State0
1State1
(1) State0/State1 selection is valid for both outputs of the corresponding PLL module and can be power down, 3-state, low, or active.
Table 7-5 Y1 Setting(1)
Y1 SELECTION
Y1FUNCTION
0State 0
1State 1
(1) State0 and State1 are user definable in the generic configuration register and can be power down, 3-state, low, or active.

S1/SDA and S2/SCL pins of the CDCE913 or CDCEL913 are dual-function pins. In the default configuration, the pins are defined as SDA/SCL for the serial programming interface. The pins can be programmed as control pins (S1/S2) by setting the appropriate bits in the EEPROM. Changes to the control register (Bit [6] of byte 02h) have no effect until the pins are written into the EEPROM.

After the S1/SDA and S2/SCL pins are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin. S0 is a control pin only.