JAJSRP6A October   2023  – May 2024 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Nomenclature
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Requirements
    7. 7.7 Timing Requirements
  9. 8 Timing Diagrams
  10. 9 Typical Characteristics
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Input Voltage (VDD)
        1. 10.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 10.3.1.2 Power-On Reset (VDD < VPOR )
      2. 10.3.2 SENSE
        1. 10.3.2.1 Reverse Polarity Protection
        2. 10.3.2.2 SENSE Hysteresis
      3. 10.3.3 Output Logic Configurations
        1. 10.3.3.1 Open-Drain
        2. 10.3.3.2 Active-Low (RESET)
        3. 10.3.3.3 Latching
        4. 10.3.3.4 UVBypass
      4. 10.3.4 User-Programmable Reset Time Delay
        1. 10.3.4.1 Reset Time Delay Configuration
      5. 10.3.5 User-Programmable Sense Delay
        1. 10.3.5.1 Sense Time Delay Configuration
      6. 10.3.6 Built-In Self-Test
    4. 10.4 Device Functional Modes
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Adjustable Voltage Thresholds
    3. 11.3 Typical Application
      1. 11.3.1 Design 1: Off-Battery Monitoring
        1. 11.3.1.1 Design Requirements
        2. 11.3.1.2 Detailed Design Procedure
          1. 11.3.1.2.1 Setting Voltage Threshold
          2. 11.3.1.2.2 Meeting the Sense and Reset Delay
          3. 11.3.1.2.3 Setting Supply Voltage
          4. 11.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 11.3.1.3 Application Curves
    4. 11.4 Power Supply Recommendations
      1. 11.4.1 Power Dissipation and Device Operation
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

10.4 Device Functional Modes

Table 10-2 Undervoltage Detect Functional Mode Truth Table
DESCRIPTIONSENSECTR (1) / MR PINVDD PINOUTPUT (2)
(RESET PIN)
PREVIOUS CONDITIONCURRENT CONDITION
Normal OperationSENSE > VITNSENSE > VITNOpen or capacitor connectedVDD > VDD(MIN)High
Undervoltage DetectionSENSE > VITNSENSE < VITNOpen or capacitor connectedVDD > VDD(MIN)Low
Undervoltage DetectionSENSE < VITNSENSE > VITNOpen or capacitor connectedVDD > VDD(MIN)Low
Normal OperationSENSE < VITNSENSE > VITN + HYSOpen or capacitor connectedVDD > VDD(MIN)High
UVLO EngagedSENSE > VITNSENSE > VITNOpen or capacitor connectedVPOR < VDD < VDD(MIN)Low
Below VPOR, Undefined OutputSENSE > VITNSENSE > VITNOpen or capacitor connectedVDD < VPORUndefined
(1) Reset time delay is ignored in the truth table.
(2) Open-drain active low output requires an external pull-up resistor to a pull-up voltage.
Table 10-3 Overvoltage Detect Functional Mode Truth Table
DESCRIPTIONSENSECTR (1) / MR PINVDD PINOUTPUT (2)
(RESET PIN)
PREVIOUS CONDITIONCURRENT CONDITION
Normal OperationSENSE < VITNSENSE < VITNOpen or capacitor connectedVDD > VDD(MIN)High
Overvoltage DetectionSENSE < VITNSENSE > VITNOpen or capacitor connectedVDD > VDD(MIN)Low
Overvoltage DetectionSENSE > VITNSENSE < VITNOpen or capacitor connectedVDD > VDD(MIN)Low
Normal OperationSENSE > VITNSENSE < VITN - HYSOpen or capacitor connectedVDD > VDD(MIN)High
UVLO EngagedSENSE < VITNSENSE < VITNOpen or capacitor connectedVPOR < VDD < UVLOLow
Below VPOR, Undefined OutputSENSE < VITNSENSE < VITNOpen or capacitor connectedVDD < VPORUndefined
(1) Reset time delay is ignored in the truth table.
(2) Open-drain active low output requires an external pull-up resistor to a pull-up voltage.