JAJSRP9 September   2024

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 説明
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Rating
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Frequency Modulation (PFM)
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Low Dropout Operation (100% Duty Cycle)
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Power Good (PG)
      4. 7.4.4 Voltage Setting and Mode Selection (VSET/MODE)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 7.5.3 HS Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register 1
    4. 8.4 VOUT Register 2
    5. 8.5 CONTROL Register
    6. 8.6 STATUS Register
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting The Output Voltage
        3. 9.2.2.3 Output Filter Design
        4. 9.2.2.4 Inductor Selection
        5. 9.2.2.5 Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Capacitor Selection

The input capacitor is the low-impedance energy source for the converters, which helps to provide stable operation. TI recommends a low-ESR multilayer ceramic capacitor for the best filtering and must be placed between VIN and GND as close as possible to those pins. For most applications, 10μF of effective(1) capacitance is sufficient, however, a larger value reduces input current ripple.

The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep the low resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends using X7R or X5R dielectrics. For operations up to 6A output current, the recommended typical output capacitor value is 30μF of effective capacitance. For operations up to 10A output current, the recommended typical output capacitor value is 55μF of effective capacitance. Values over 200µF can degrade the loop stability of the converter.

The effective capacitance is the capacitance after tolerance, temperature, and DC bias effects have been considered.