JAJSRP9
September 2024
ADVANCE INFORMATION
1
1
特長
2
アプリケーション
3
説明
4
Device Options
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Rating
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Pulse Frequency Modulation (PFM)
7.3.2
Forced PWM Mode
7.3.3
Low Dropout Operation (100% Duty Cycle)
7.3.4
Soft Start
7.3.5
Switch Current Limit and HICCUP Short-Circuit Protection
7.3.6
Undervoltage Lockout
7.3.7
Thermal Warning and Shutdown
7.4
Device Functional Modes
7.4.1
Enable and Disable (EN)
7.4.2
Output Discharge
7.4.3
Power Good (PG)
7.4.4
Voltage Setting and Mode Selection (VSET/MODE)
7.5
Programming
7.5.1
Serial Interface Description
7.5.2
Standard-, Fast-, and Fast-Mode Plus Protocol
7.5.3
HS Mode Protocol
7.5.4
I2C Update Sequence
7.5.5
I2C Register Reset
8
Register Map
8.1
Target Address Byte
8.2
Register Address Byte
8.3
VOUT Register 1
8.4
VOUT Register 2
8.5
CONTROL Register
8.6
STATUS Register
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Custom Design With WEBENCH® Tools
9.2.2.2
Setting The Output Voltage
9.2.2.3
Output Filter Design
9.2.2.4
Inductor Selection
9.2.2.5
Capacitor Selection
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
9.4.2.1
Thermal Considerations
10
Device and Documentation Support
10.1
Device Support
10.1.1
サード・パーティ製品に関する免責事項
10.1.2
Development Support
10.1.2.1
Custom Design With WEBENCH® Tools
10.2
Documentation Support
10.2.1
Related Documentation
10.3
ドキュメントの更新通知を受け取る方法
10.4
サポート・リソース
10.5
Trademarks
10.6
静電気放電に関する注意事項
10.7
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
7.4
Device Functional Modes