JAJSS25C
February 2019 – January 2024
UCC21732-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Power Ratings
5.6
Insulation Specifications
5.7
Safety-Related Certifications
5.8
Safety Limiting Values
5.9
Electrical Characteristics
5.10
Switching Characteristics
5.11
Insulation Characteristics Curves
5.12
Typical Characteristics
6
Parameter Measurement Information
6.1
Propagation Delay
6.1.1
Regular Turn-OFF
6.2
Input Deglitch Filter
6.3
Active Miller Clamp
6.3.1
External Active Miller Clamp
6.4
Under Voltage Lockout (UVLO)
6.4.1
VCC UVLO
6.4.2
VDD UVLO
6.5
OC (Over Current) Protection
6.5.1
OC Protection with 2-Level Turn-OFF
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Supply
7.3.2
Driver Stage
7.3.3
VCC and VDD Undervoltage Lockout (UVLO)
7.3.4
Active Pulldown
7.3.5
Short Circuit Clamping
7.3.6
External Active Miller Clamp
7.3.7
Overcurrent and Short Circuit Protection
7.3.8
2-Level Turn-Off
7.3.9
Fault ( FLT, Reset and Enable ( RST/EN)
7.3.10
Isolated Analog to PWM Signal Function
7.4
Device Functional Modes
8
Applications and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input Filters for IN+, IN- and RST/EN
8.2.2.2
PWM Interlock of IN+ and IN-
8.2.2.3
FLT, RDY and RST/EN Pin Circuitry
8.2.2.4
RST/EN Pin Control
8.2.2.5
Turn-On and Turn-Off Gate Resistors
8.2.2.6
External Active Miller Clamp
8.2.2.7
Overcurrent and Short Circuit Protection
8.2.2.7.1
Protection Based on Power Modules with Integrated SenseFET
8.2.2.7.2
Protection Based on Desaturation Circuit
8.2.2.7.3
Protection Based on Shunt Resistor in Power Loop
8.2.2.8
Isolated Analog Signal Sensing
8.2.2.8.1
Isolated Temperature Sensing
8.2.2.8.2
Isolated DC Bus Voltage Sensing
8.2.2.9
Higher Output Current Using an External Current Buffer
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
サード・パーティ製品に関する免責事項
11.2
Documentation Support
11.2.1
Related Documentation
11.3
ドキュメントの更新通知を受け取る方法
11.4
サポート・リソース
11.5
Trademarks
11.6
静電気放電に関する注意事項
11.7
用語集
12
Revision History
13
Mechanical, Packaging, and Orderable Information
5.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±4000
V
Charged-device model (CDM), per AEC Q100-011
±1500
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.