JAJSSI7J August   2001  – December 2023 UCC29002 , UCC39002

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Differential Current-Sense Amplifier (CS+, CS−, CSO)
      2. 6.3.2 Load-Share Bus Driver Amplifier (CSO, LS)
      3. 6.3.3 Load-Share Bus Receiver Amplifier (LS)
      4. 6.3.4 Error Amplifier (EAO)
      5. 6.3.5 Adjust Amplifier Output (ADJ)
      6. 6.3.6 Enable Function (CS+, CS−)
      7. 6.3.7 Fault Protection on LS Bus
      8. 6.3.8 Start-Up and Adjust Logic
      9. 6.3.9 Bias Input and Bias_OK Circuit (VDD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Start-Up Mode
      2. 6.4.2 Normal Running Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Disabled Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Paralleling the Power Modules
    3. 7.3 Typical Application
      1. 7.3.1 Measuring the Voltage Loop of a Power Module
      2. 7.3.2 Detailed Design Procedure
        1. 7.3.2.1 The Shunt Resistor
        2. 7.3.2.2 The CSA Gain
        3. 7.3.2.3 Determining RADJ
        4. 7.3.2.4 Error Amplifier Compensation
      3. 7.3.3 Application Curve
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
      1. 8.1.1 Documentation Support
    2. 8.2 Related Links
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9Revision History
  11.   Mechanical, Packaging, and Orderable Information

7.2 Paralleling the Power Modules

The symbols used in this section are defined as:

    VOUTThe nominal output voltage of the modules to be paralleled.
    IOUT(max)The maximum output current of each module to be paralleled.
    ΔVADJ(max) The maximum output voltage adjustment range of the power modules to be paralleled.
    NmThe number of power modules to be paralleled.
Note:

The power modules to be paralleled must be equipped with true remote-sense inputs or with access to the feedback divider network of the module’s error amplifier.

Figure 7-1 shows a typical high-side current-sense configuration for a single module which is repeated for each module to be paralleled. Direct connection of the VDD pin to the power module VOUT rail (V+) is valid for VOUT less than 13.5V.

GUID-AF1941A6-E042-4326-A817-FFD8800140CA-low.gif Figure 7-1 Typical High-Side Application for a Single Power Module

In Figure 7-1, P1 represents the output-voltage connector terminals of the module and S1 represents the remote-sense connector terminals of the module. In this example, a signal on the SB2 terminal enables the disconnect feature of the device. The Load-Share Bus is the common bus between all of the paralleled load-share controllers. The VDD supply must be decoupled with a good-quality ceramic capacitor returned directly to GND.

For applications where the module output voltage is higher than the maximum VDD rating, it is best practice to configure RSHUNT in the GND-return rail as shown in Figure 7-2. The VCC pin is biased from VOUT using dropping resistor RBIAS1 to limit current and the ADJ pin is buffered from VOUT by an NPN transistor.

GUID-E4328B46-570B-4661-86D3-221EE2EB3383-low.gif Figure 7-2 High-Voltage Application with Low-side Current-Sensing