JAJSSQ9 June   2024

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 Forced PWM Mode
      3. 7.3.3 Optimized Transient Performance from PWM to PSM Operation
      4. 7.3.4 Low Dropout Operation (100% Duty Cycle)
      5. 7.3.5 Enable and Soft-Start Ramp
      6. 7.3.6 Switch Current Limit and HICCUP Short-Circuit Protection
      7. 7.3.7 Undervoltage Lockout
      8. 7.3.8 Thermal Warning and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Disable (EN)
      2. 7.4.2 Output Discharge
      3. 7.4.3 Start-Up Output Voltage and I2C Target Address Selection (VSET)
      4. 7.4.4 Select Output Voltage Registers (VID)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-Mode, Fast-Mode, and Fast-Mode Plus Protocol
      3. 7.5.3 HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Register Map
    1. 8.1 Target Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register 1
    4. 8.4 VOUT Register 2
    5. 8.5 CONTROL Register
    6. 8.6 STATUS Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.3 Optimized Transient Performance from PWM to PSM Operation

For most converters, the load transient response in PWM mode is improved compared to PSM, because the converter reacts faster on the load step and actively sinks energy on the load release. As an additional feature, the TPSM8286xx automatically stays in PWM mode for 128 cycles after a heavy load release to bring the output voltage back to the regulation level faster. After these 128 cycles of PWM mode, the device automatically returns to PSM (if the Enable FPWM Mode bit = 0). See Figure 7-1. Without this optimization, the output voltage overshoot is higher.

TPSM82866C Optimized Transient Performance from PWM to PSM Figure 7-1 Optimized Transient Performance from PWM to PSM