JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.1.1 Design Requirements

This design requires voltage sequencing of four voltage rails. The nominal TPS7H3014 input voltage is 12V and the sequencer is set to start the sequence up and down automatically when the voltage reaches the desired target voltage levels. All the voltage regulators are powered by a nominal 5V voltage rail. The system housekeeping microcontroller can monitor a fault via the voltage at the FAULT pin, which is pulled-up to VLDO. The PWRGD is the flag to be connected to the non-maskable interrupt of the system if it exists, or monitored by the MCU to know the status of the power tree. The SEQ_DONE can also be monitored to know if the sequence up/down are completed. All design conditions are defined in Table 9-1.

Table 9-1 Design Conditions
PARAMETERDESIGN REQUIREMENTDESIGN RESULT
System nominal voltage Monitor the 12V input voltage and start the sequence up when the voltage is greater than 10.7V (88%) for at least 3.7ms. When the voltage decrements below 6V (or 50%) a sequence down is started. The TPS7H3014 can monitor a voltage and start a sequence up and down automatically via a resistive divider. The internal reference in UP and DOWN have an accuracy of 3%. For minimal error, it is recommended to use 0.1% tolerance resistors.
VOUT13.3V nominal with:

VON = 90% and VOFF = 10%

VON = 2.978V ±29.97mV

VOFF = 0.338V ±84.61mV

Using 0.1% tolerance resistors

VOUT20.8V nominal with:

VON = 90% and VOFF = 10%

VON = 0.722V ±7.22 mV

VOFF = 0.081V ±20.54mV

Using 0.1% tolerance resistors

VOUT31.5V nominal with:

VON = 90% and VOFF = 10%

VON = 1.343V ±13.47mV

VOFF = 0.145V ±38.35mV

Using 0.1% tolerance resistors

VOUT40.88V nominal with:

VON = 90% and VOFF = 10%

VON = 0.793V ±7.93mV

VOFF = 0.087V ±22.6mV

Using 0.1% tolerance resistors

ENx delay during sequence up and down Delay of 0.268ms nominalRDLY_TMR = 10.4kΩ
Allowed time for a rail to reach the VONxAllow 10.3ms (nominal) for the rail to reach the VONxRREG_TMR = 511kΩ