JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.2.1 VTH_SENSEX and VONx

The TPS7H3014 sequencer integrates four under-voltage (UV) comparators, with an accurate (±1%) threshold voltage (VTH_SENSEx) of 599mV nominal. VTH_SENSEx is measured at the ENx outputs to account for comparator offsets in the threshold. Maximum flexibility is provided as external resistive dividers can be adjusted to sense any voltage rail (VOUTx). Figure 8-2 shows a conceptual diagram of the comparators connected to the SENSEx inputs. As can be observed, the sensed voltage rail (VOUTx) is attenuated (using an external resistive divider, RTOPx and RBOTTOMx) and compared against the VTH_SENSEx voltage. Is recommended to maintain the steady-state SENSEx voltage below 1.6V, in order to maintain the threshold (VTH_SENSEx) accuracy.

TPS7H3014-SP SENSEx Comparators Inputs Figure 8-2 SENSEx Comparators Inputs

When the voltage at the monitored rail (VOUTx) is rising, the hysteresis current (IHYS) is not connected to SENSEx input. At this time the SENSEx (attenuated VOUTx) voltage is compared against the SENSEx threshold (VTH_SENSEx). When VSENSEx > VTH_SENSEx the voltage is considered within regulation limits. We can calculate the on (within regulation) voltage by doing a simple voltage divider as:

Equation 1. V O N x _ N O M I N A L   ( V )   =   1 + R T O P x R B O T T O M x × V T H _ S E N S E x

Where:

  • VTH_SENSEx is the nominal sense threshold voltage of 599mV.

As with any system, there is some variation (or errors) of the design variables, in this case the top and bottom resistors and the SENSEx threshold voltage. Using the derivative method to calculate the total error (and assuming these variables are uncorrelated) with both resistors having the same tolerance value, the VONx error can be calculated as:

Equation 2. V O N x _ E R R O R   ( V )   = ± V T H _ S E N S E x 2 × 2 × R T O L 2 × R T O P x 2 + V T H _ S E N S E x _ A C C 2 × R T O P x + R B O T T O M x 2 R B O T T O M x 2

Where:

  • RTOL is the resistors tolerance (same for top and bottom resistors) as numeric value. For example, for 0.1% tolerance resistors, we use 0.001.
  • VTH_SENSEx_ACC is the SENSEx threshold accuracy as numeric value (in this case 0.01).
  • RTOPx and RBOTTOMx are in Ohms (Ω).
  • VTH_SENSEx is 0.599 Volts.

Using Equation 1 and Equation 2 we can calculate the on voltage range as:

Equation 3. V O N x = V O N x _ N O M I N A L   ±   V O N x _ E R R O R

Note: Remember VTH_SENSEx is the reference voltage when accounting for the comparator offsets VTH_SENSEx = VREF + VOFFSETx.

As this device is intended for sequencing of multirail systems, the ENx to SENSEx order is defined in ascending channel number (EN1 to EN4) for sequence up, and descending (EN4 to EN1) for sequence down. When a channel of the sequencer is not needed (unused) the channel can be connected to VLDO to skip the channel during sequence up/down. Is recommended to connect all disabled channels to VLDO, but an external voltage greater than 91% of VLDO (max) will disabled the channel (the voltage at SENSEx cannot exceed 3.5V). Only channels 2 through 4 can be disabled. It is recommended to disabled channels starting from high (channel #4) to low (channel #2). The channels are disabled starting from the lowest channel count and higher. This means that if channel #2 is disabled, by definition channels #3 and #4 will also be disabled.

Note: The channels to be disabled must be valid at power up and not be dynamically changed during the sequence up and down.

Any voltage at SENSE 2 to SENSE4 > VTURN_OFF [91% of VLDO(max)] will disable (or turn-off) the channel. This will disable the delay (set by TMR_DLY) for those channels during sequence up and down.

Although it is not required, in noisy applications it is good analog design practice to place a small bypass capacitor at the SENSEx inputs in order to reduce sensitivity to transient voltages on the monitored signal.