JAJSSS6B January 2024 – June 2024 TPS7H3014-SP
PRODUCTION DATA
The output stage's (EN1 to EN4), SEQ_DONE and PWRGD are of push-pull, active high type. The pull-up voltage for the push-pull outputs is externally provided by the user. PULL_UP1 (input) is the pull-up voltage domain for all ENx outputs (EN1 to EN4), while PULL_UP2 (input) is the pull-up voltage domain for the SEQ_DONE and PWRGD outputs.
Each output stage consists of a PMOS/NMOS (CMOS) pair. Each leg has an output resistance of typically 7Ω for VPULL_UPx > 3.3V. PULL_UP1 and PULL_UP2, have a voltage range of 1.6V~7V, and can be independently biased or tied to the same voltage rail, however both most be biased. The output resistance of the PMOS leg has a PULL_UPx voltage dependency. The lower the PULL_UPx voltage, the higher the PMOS resistance.
When VIN < VPOR_IN and VPULL_UPx > VPOR_PULL_UPx (1.4V maximum) the output will be in a known pull-down state. At this condition the outputs have reduced sinking capabilities with VOL ≤ 320mV when the device is sinking 100μA of current into the outputs:
Once the input voltage range is withing the recommended input voltage range of 3V to 14V, the output will have the full strength capabilities of ±10mA, per output.