JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.1.2 Power-On Reset (VIN < VPOR_IN )

When the voltage on VIN is lower than the power on reset voltage (VPOR_IN), the output signal is undefined and is not to be relied upon for proper device function.

Figure 8-1 shows the ENx outputs relationship to a rising input voltage (VIN). As can be observed, the ENx are undefined when VIN is lower than VPOR_IN (typically 1.41V). During this time the outputs can be any value from 0V to VIN. In this case, the input voltages to all undervoltage (UV) input comparators (SENSEx) are below the VTH_SENSEx (599mV). For this reason (in conjunction with waiting for a rising edge on UP), the ENx, SEQ_DONE and PWRGD stays low after VIN rises above UVLORISE (typically 2.79V).

TPS7H3014-SP Outputs in a Valid Low State After VIN > VIN-MIN Figure 8-1 Outputs in a Valid Low State After VIN > VIN-MIN
A. This figures assumes:
  1. A valid external pull-up voltage is connected to the PULL_UPx inputs (1.6V ≤ VPULL_UPx ≤ 7V).
  2. VIN(STEADY-SATE) is a valid VIN voltage between 3V to 14V.
  3. VFAULT pull up to VLDO.
  4. Device is in the: Waiting to Sequence UP State (Refer to State Machine for more details).
  5. VOL represents: VOL_ENx, VOL_SEQ_DONE, and VOL_PWRGD, or the low logic output voltage for all outputs.