JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.7 State Machine

The TPS7H3014 incorporates a comprehensive state machine engine. Three possible outcomes are possible depending on the detected inputs states.

  1. A reverse sequence down from previously deemed-good (forced high) ENx signals, is started if:
    • VOUTx fails to reach the VONx voltage during sequence up within the time establish by the REG_TMR, when ENx is high.
    • Any VOUTx crosses the VOFFx after previously crossing the VONx and the VOUTx+1 has not yet crossed the VONx+1.
    • The users command a sequence down in the middle of a sequence up.
  2. All outputs (ENx, SEQ_DONE and PWRGD) are forced low if an out-of-order is detected, this means:
    • A previously deemed-good rail VOUTx drops below VOFFx when at least the VOUTx+1 is already in regulation (deemed-good).
    • Any VOUTx > VONx when ENX is not high. Valid only during sequence up.
      Note:

      It is typical in sequencers to set VONx as some percentage of the nominal voltage to be monitored (E.g. VONx = 0.8 × VOUTx). There is a period of time during sequence down at which the VOUTx ≥ VONx. As the discharge rate of the rail (VOUTx) is unknown to the TPS7H3014, this feature is only valid during sequence up.

  3. A sequence up from previously forced low ENx signals, after the DLY_TMR is expired is started if:
    • The users command a sequence up in the middle of a sequence down.
TPS7H3014-SP TPS7H3014 State Machine Diagram Figure 8-14 TPS7H3014 State Machine Diagram