JAJSSS6B
January 2024 – June 2024
TPS7H3014-SP
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Options
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Quality Conformance Inspection
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Input Voltage (IN), VLDO and REFCAP
8.3.1.1
Undervoltage Lockout (VPOR_IN < VIN < UVLO)
8.3.1.2
Power-On Reset (VIN < VPOR_IN )
8.3.2
SENSEx Inputs
8.3.2.1
VTH_SENSEX and VONx
8.3.2.2
IHYS_SENSEx and VOFFx
8.3.2.3
Top and Bottom Resistive Divider Design Equations
8.3.3
Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
8.3.4
User-Programmable TIMERS
8.3.4.1
DLY_TMR
8.3.4.2
REG_TMR
8.3.5
UP and DOWN
8.3.6
FAULT
8.3.7
State Machine
8.4
Daisy Chain
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Self Contained – Sequence UP and DOWN
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Input Power Supplies and Decoupling Capacitors
9.2.1.2.2
UP and DOWN Thresholds
9.2.1.2.3
SENSEx Thresholds
9.2.1.3
Application Curves
9.2.2
Sequencing of Negative Voltage Rails
9.2.2.1
Negative Voltage Design Equations
9.3
Externally Induced System RESET
9.4
Power Supply Recommendations
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
9.2.1.3
Application Curves
Figure 9-2
V
IN
vs Time During Sequence UP
Figure 9-3
EN1 and V
OUT1
vs Time During Sequence UP
Figure 9-4
EN2 and V
OUT2
vs Time During Sequence UP
Figure 9-5
EN3 and V
OUT3
vs Time During Sequence UP
Figure 9-6
EN4 and V
OUT4
vs Time During Sequence UP
Figure 9-7
PWRGD and SEQ_DONE vs Time During Sequence UP
Figure 9-8
V
IN
vs Time During Sequence DOWN
Figure 9-9
PWRGD and SEQ_DONE vs Time During Sequence DOWN
Figure 9-10
EN4 and V
OUT4
vs Time During Sequence DOWN
Figure 9-11
EN3 and V
OUT3
vs Time During Sequence DOWN
Figure 9-12
EN2 and V
OUT2
vs Time During Sequence DOWN
Figure 9-13
EN1 and V
OUT1
vs Time During Sequence DOWN