JAJSSS6B January   2024  – June 2024 TPS7H3014-SP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN )
      2. 8.3.2 SENSEx Inputs
        1. 8.3.2.1 VTH_SENSEX and VONx
        2. 8.3.2.2 IHYS_SENSEx and VOFFx
        3. 8.3.2.3 Top and Bottom Resistive Divider Design Equations
      3. 8.3.3 Output Stages (ENx,SEQ_DONE,PWRGD,PULL_UP1 and PULL_UP2)
      4. 8.3.4 User-Programmable TIMERS
        1. 8.3.4.1 DLY_TMR
        2. 8.3.4.2 REG_TMR
      5. 8.3.5 UP and DOWN
      6. 8.3.6 FAULT
      7. 8.3.7 State Machine
    4. 8.4 Daisy Chain
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Self Contained – Sequence UP and DOWN
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 UP and DOWN Thresholds
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sequencing of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Design Equations
    3. 9.3 Externally Induced System RESET
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.4.1 DLY_TMR

The TPS7H3014 includes an adjustable time delay. A single resistor connected between the DLY_TMR pin and GND will program the delay. Possible resistor (RDLY) values are between 10.5kΩ and 1.18MΩ for a 268μs to 23.63ms delay, respectively. During sequence up, this delay holds the ENx+1, SEQ_DONE, and PWRGD low after the monitored voltage crosses the "on" voltage (VOUTx > VONx) for the user programmed time. During sequence down, the ENx–1 and SEQ_DONE are held high for the programmed delay time after the monitored voltage crosses the "off" voltage (VOUTx < VOFFx).
Note: During sequence down, PWRGD goes low immediately after the VDOWN < VTH_DOWN.

If no delay is preferred for the system, the pin (DLY_TMR) can be left floating. When no delay is preferred, an inherent propagation delay of 6.5μs (max) will be observed during sequence up, between VOUTx crossing the VONx and ENx+1 going high. The propagation delay is also observed during sequence down when VOUTx cross the VOFFx and the ENx–1 is forced low. SEQ_DONE and PWRGD also have this propagation delay during VOUT4 > VON4 during sequence up. During sequence down, SEQ_DONE will go low after the propagation delay when VOUT1 < VOFF1 and PWRGD will go low after the propagation delay when the sequence down is commanded. Figure 8-8 shows the propagation delay in blue (tpd_ENx, tpd_SEQ_DONE, tpd_PWRGD) and the programmed delay (tDLY_TMR) in orange. The DLY_TMR resistor can be selected using Equation 15 or Equation 16. Figure 8-9 and Figure 8-10 shows the linear trend between the DLY_TMR resistor and the delay time.

For tDLY_TMR between 0.268ms and 12.5ms use:

Equation 15. R D L Y _ T M R ( k Ω ) = 49.75 × t D L Y _ T M R   ( m s ) - 2.832

For tDLY_TMR greater than 12.5ms use:

Equation 16. R D L Y _ T M R ( k Ω ) = 51.61 × t D L Y _ T M R   ( m s ) - 26.12

Table 8-1 shows nominal resistors value for different delay times.

Table 8-1 Typical DLY_TMR Resistors
tDLY_TMR (ms) RDLY_TMR (kΩ)
0.268 10.5
12.5 619
23.37 1180
TPS7H3014-SP RDLY_TMR vs tDLY_TMR From 0.268ms to 12.5msFigure 8-9 RDLY_TMR vs tDLY_TMR From 0.268ms to 12.5ms
TPS7H3014-SP RDLY_TMR vs tDLY_TMR From 12.5ms to 23.37msFigure 8-10 RDLY_TMR vs tDLY_TMR From 12.5ms to 23.37ms