JAJSSZ8T January   2015  – September 2024 SN74LVC125A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
      3. 8.1.3 Application Curves
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.1.2 Detailed Design Procedure

  1. Recommended Input Conditions:
    • For rise time and fall time specifications, see (Δt/ΔV) in the Section 5.3 table.
    • For specified high and low levels, see (VIH and VIL) in the Section 5.3 table.
    • Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Section 5.3 table at any valid VCC.
  2. Recommend Output Conditions:
    • Load currents should not exceed (IO max) per output and should not exceed (Continuous current through VCC or GND) total current for the part. These limits are located in the Section 5.1 table.
    • Outputs should not be pulled above VCC.
    • Series resistors on the output may be used if the user desires to slow the output edge signal or limit the output current.