JAJSTC8A February 2024 – April 2024 LP5867
PRODUCTION DATA
The address and data bits are transmitted MSB first with 8-bits length format in each cycle. Each transmission is started with Address Byte 1, which are divided into 5-bits of the chip address, 2 higher bits of the register address, and 1 read/write bit. The other 8 lower bits of register address are put in Address Byte 2.The device supports both independent mode and broadcast mode. The auto-increment feature allows writing / reading several consecutive registers within one transmission. If not consecutive, a new transmission must be started.
Address Byte1 | Chip Address | Register Address | R/W | |||||
---|---|---|---|---|---|---|---|---|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |
Independent | 1 | 0 | 0 | ADDR1 | ADDR0 | 9th bit | 8th bit | R: 1 W: 0 |
Broadcast | 1 | 0 | 1 | 0 | 1 | |||
Address Byte2 | Register Address | |||||||
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |
7th bit | 6th bit | 5th bit | 4th bit | 3th bit | 2th bit | 1th bit | 0th bit |