JAJSTC8A February 2024 – April 2024 LP5867
PRODUCTION DATA
When selecting data refresh Mode 1, outputs are refreshed instantly after data is received.
When selecting data refresh Mode 2/3, VSYNC signal is required for synchronized display. Programming flow is showed as Figure 9-2. To display full pixel of last frame, VSYNC pulse must be sent to the device after the end of last PWM. Time between two pulses tSYNC must be larger than the whole PWM time of all Dots tframe. Common selection like 60Hz, 90Hz, 120Hz or even higher refresh frequency can be supported. High pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame, and data must not be write to PWM registers during high pulse width.