JAJSTM8 April 2024 AFE20408
PRODUCTION DATA
The DAC produces unipolar output voltages proportional to a 13-bit input data code. Input data are written to the DAC data register in straight binary format for all output ranges.
The DAC transfer function is given by:
where
The DAC output spans the voltage ranges shown in Table 6-5.
DAC DATA REGISTER | DAC OUTPUT VOLTAGE (V) | ||
---|---|---|---|
BINARY | HEX | 0V to 10V RANGE VCC = 11V VSS = GND | –10V to 0V RANGE VSS = –11V VCC = GND |
0000 0000 0000 0000 | 0000 | 0 | –10 |
0000 0000 0000 0001 | 0001 | 0.001221 | –9.998779 |
0001 0000 0000 0000 | 1000 | 5 | –5 |
0001 1111 1111 1110 | 1FFE | 9.997559 | –0.002441 |
0001 1111 1111 1111 | 1FFF | 9.998779 | –0.001221 |
By setting the corresponding BCEN bits in the DAC_SYNC_CFG register (located in the DAC configuration register page), each DAC can be configured to operate in broadcast mode. When a value is written to the DAC_BCAST register (in the global register page), this value is automatically stored in the buffer and active data registers of all DACs operating in broadcast mode. Additionally, a DAC code limit feature is included, which can be used to digitally limit the DAC code to one of 64 different limits. When enabled, a limit is placed on the upper six bits of the DAC code written to the data registers. The limit is only enforced on the DAC active register, and on codes which are written after the DAC code limit has been set to a code less than full scale. The user needs to configure the DAC code limit register, and then subsequent DAC writes are subjected to the currently set DAC code limit. Code limits are specified by writing to the DAC_CODE_LIMIT registers in the DAC Configuration register page (see Section 7.5 for more details).