JAJSTW2D January   2024  – June 2024 UCC33420-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Insulation Specifications
    6. 5.6 Safety-Related Certifications
    7. 5.7 Electrical Characteristics
    8. 5.8 External BOM Components
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Disable
      2. 6.3.2 Output Voltage Soft-Start and Steady-State Regulation
      3. 6.3.3 Protection Features
        1. 6.3.3.1 Input Under-voltage and Over-Voltage Lockout
        2. 6.3.3.2 Output Under-Voltage Protection
        3. 6.3.3.3 Output Over-Voltage Protection
        4. 6.3.3.4 Over-Temperature Protection
        5. 6.3.3.5 Fault Reporting and Auto-Restart
      4. 6.3.4 VCC Output Voltage Selection
      5. 6.3.5 VCC Load Recommended Operating Area
      6. 6.3.6 Electromagnetic Compatibility (EMC) Considerations
    4. 6.4 Device Functional Modes
    5. 6.5 Pre-Production Samples Operating Limits
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical and Packaging Information

5.7 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 150°C), VINP = 5.0V, CIN1 =  COUT1 = 2.2nF, CIN2 = 10µF, COUT2 = 22µF, SEL connected to VCC, EN/FLT = 5.0V unless otherwise noted. All typical values at VINP=5.0V, TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (Primary-side. All voltages with respect to GNDP)
IVINP_Q VINP quiescent current,disabled EN/FLT=Low, VINP=5.0V, no load 180 µA
IVINP_NL VINP operating current, no load EN/FLT=High; VINP=4.5V-5.5V; VCC=5.0V no load 7 15 mA
EN/FLT=High; VINP=4.5V-5.5V; VCC=5.5V no load 7 15 mA
IVINP_FL VINP operating current, full load EN/FLT=High; VINP=5.0V; VCC=5.0V, Iout=300mA, TA=25°C 535 mA
UVLOP COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVINP_UVLO_R VINP under-voltage lockout rising threshold 2.8 2.9 V
VVINP_UVLO_F VINP under-voltage lockout falling threshold 2.6 2.7 V
VUVLO_H VINP under-voltage lockout hysteresis 0.1 V
OVLO COMPARATOR (Primary-side. All voltages with respect to GNDP)
VVINP_OVLO_R VINP over-voltage lockout rising threshold 5.77 5.9 V
VVINP_OVLO_F VINP over-voltage lockout falling threshold 5.55 5.72 V
VVINP_H VINP over-voltage lockout hysteresis 0.05 V
Switching Charactarestics
fSw DC-DC Converter switching frequency 76 MHz
PRIMARY SIDE THERMAL SHUTDOWN
TSDP_R Primary-side over-temperature shutdown rising threshold 150 165 ºC
TSDP_F Primary-side over-temperature shutdown falling threshold 130 ºC
TSDP_H Primary-side over-temperature shutdown hysteresis 20 ºC
EN/FLT PIN
VEN_R Enable voltage rising threshold EN/FLT = 0V to 5.0V  2.1 V
VEN_F Enable voltage falling threshold EN/FLT = 5.0V to 0V 0.8 V
IEN Enable pin input Current EN/FLT = 5.0V 10 µA
VFLT EN/FLT pin voltage when faults occur With a minimum 18kohm (10% tolerance) resistor connected to EN/FLT pin  0.5 V
tFault EN/FLT pull down interval when faults occur EN/FLT > 0.5V , Fault occur  200 µs
VCC OUTPUT VOLTAGE (Secondary-side. All voltages with respect to GNDS)
VCC Isolated supply regulated output voltage VINP = 5.0V; VCC = 5.0V, Iout = 0 - 300mA 4.85 5 5.15 V
VINP = 5.0V; VCC = 5.5V, Iout = 0 - 200mA 5.34 5.5 5.67 V
Isolated supply regulated output voltage accuracy VINP = 4.5V - 5.5V; VCC = 5.0V / 5.5V -4 4 %
VCC_Line Vcc DC line regulation VINP = 4.5V - 5.5V; VCC =5.0V, Iout = 150mA 2 mV/V
VINP = 4.5V - 5.5V; VCC = 5.5V, Iout = 150mA 2 mV/V
VCC_Load Vcc DC load regulation VINP = 5.0V; VCC = 5.0V, Iout = 0-300mA 0.5%
VINP = 5.0V; VCC = 5.5V, Iout = 0-200mA 0.5%
VCC_Ripple Voltage ripple on isolated supply output 20-MHz bandwidth, VINP = 5.0V , VCC = 5.0V, Iout = 300mA, TA=25°C 50 75 mV
EFF Efficiency PVCC to PVINP  VINP = 5.0V, VCC = 5.0V, Iout = 300mA, TA = 25°C 55 %
VCC_Rise VCC rise time from 10% - 90% VINP = 4.5V - 5.5V, VCC = 5.0V, Iout = 70mA  500 µs
VINP = 4.5V - 5.5V, VCC = 5.5V, Iout = 70mA  500 µs
VCC UVP UNDER -VOLTAGE PROTECTION (Secondary-side. All voltages with respect to GNDS)
KVCC_UVP VCC under-voltage protection threshold ratio VUVP = VCC * 90% 90 %
VUVP_H VCC under-voltage protection hysteresis VCC = 5.0V 79 100 121 mV
VUVP_H VCC under-voltage protection hysteresis VCC = 5.5V 87 110 133 mV
VCC OVP OVER -VOLTAGE PROTECTION (Secondary-side. All voltages with respect to GNDS)
VVCC_OVP_R VCC over-voltage protection rising threshold VCC = 5.0V 5.45 5.5 V
VVCC_OVP_H VCC over-voltage protection hysterisis VCC = 5.0V 0.1 V
VVCC_OVP_R VCC over-voltage protection rising threshold VCC = 5.5V 5.9 5.95 V
VVCC_OVP_H VCC over-voltage protection hysterisis VCC = 5.5V 0.12 V
SECONDARY SIDE THERMAL SHUTDOWN 
TSDS_R Secondary-side over-temperature shutdown rising threshold 150 165 ºC
TSDS_F Secondary-side over-temperature shutdown falling threshold 130 ºC
TSDS_H Secondary-side over-temperature shutdown hysteresis 20 ºC