JAJSU80 March 2024
ADVANCE INFORMATION
Table 6-43, Table 6-44, Figure 6-36, Table 6-45 and Figure 6-37 present timing conditions, requirements, and switching characteristics for DSS.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
INPUT CONDITIONS | ||||
SRI | Input slew rate | 1.44 | 26.4 | V/ns |
OUTPUT CONDITIONS | ||||
CL | Output load capacitance | 1.5 | 5 | pF |
PCB CONNECTIVITY REQUIREMENTS | ||||
td(Trace Mismatch Delay) | Propagation delay mismatch across all traces | 100 | ps |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
D6 | tc(extpclkin) | Cycle time, VOUT(x)_EXTPCLKIN(2) | 6.06 | ns | |
D7 | tw(extpclkinL) | Pulse duration, VOUT(x)_EXTPCLKIN(2) low | 0.475P(1) | ns | |
D8 | tw(extpclkinH) | Pulse duration, VOUT(x)_EXTPCLKIN(2) high | 0.475P(1) | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
D1 | tc(pclk) | Cycle time, VOUT(x)_PCLK(2) | 6.06 | ns | ||
D2 | tw(pclkL) | Pulse duration, VOUT(x)_PCLK(2) low | Internal PLL | 0.475P(1) - 0.3 | ns | |
EXTPCLKIN | Y(3) - 0.45 | ns | ||||
D3 | tw(pclkH) | Pulse duration, VOUT(x)_PCLK(2) high | Internal PLL | 0.475P(1) -0.3 | ns | |
EXTPCLKIN | Z(4) - 0.45 | ns | ||||
D4 | td(pclkV-dataV) | Delay time, VOUT(x)_PCLK(2) transition to VOUT(x)_DATA[23:0](2) transition | Internal PLL | -0.68 | 1.78 | ns |
EXTPCLKIN | -0.68 | 1.78 | ns | |||
D5 | td(pclkV-ctrlL) | Delay time, VOUT(x)_PCLK(2) transition to control signals VOUT(x)_VSYNC(2), VOUT(x)_HSYNC(2), VOUT(x)_DE(2) falling edge | Internal PLL | -0.68 | 1.78 | ns |
EXTPCLKIN | -0.68 | 1.78 | ns |
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter of the device TRM.