JAJSUK0
May 2024
IWR2944
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
3.1
機能ブロック図
4
Device Comparison
4.1
Related Products
5
Pin Configurations and Functions
5.1
Pin Diagram
5.2
Pin Attributes
5.3
Signal Descriptions - Digital
5.4
Signal Descriptions - Analog
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Power-On Hours (POH)
6.4
Recommended Operating Conditions
6.5
VPP Specifications for One-Time Programmable (OTP) eFuses
6.5.1
Recommended Operating Conditions for OTP eFuse Programming
6.5.2
Hardware Requirements
6.5.3
Impact to Your Hardware Warranty
6.6
Power Supply Specifications
6.7
Power Consumption Summary
6.8
RF Specifications
6.9
Thermal Resistance Characteristics
6.10
Power Supply Sequencing and Reset Timing
6.11
Input Clocks and Oscillators
6.11.1
Clock Specifications
6.12
Peripheral Information
6.12.1
QSPI Flash Memory Peripheral
6.12.1.1
QSPI Timing Conditions
6.12.1.2
QSPI Timing Requirements #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
6.12.1.3
QSPI Switching Characteristics #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-64 #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-65
6.12.2
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
6.12.2.1
MibSPI Peripheral Description
6.12.2.2
MibSPI Transmit and Receive RAM Organization
6.12.2.2.1
SPI Timing Conditions
6.12.2.2.2
SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-236 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-237 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-238
6.12.2.2.3
SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-244 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-245 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-246
6.12.2.3
SPI Peripheral Mode I/O Timings
6.12.2.3.1
SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-70 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-71 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-73
6.12.3
Ethernet Switch (RGMII/RMII/MII) Peripheral
6.12.3.1
RGMII/MII Timing Conditions
6.12.3.2
RGMII Transmit Clock Switching Characteristics
6.12.3.3
RGMII Transmit Data and Control Switching Characteristics
6.12.3.4
RGMII Receive Clock Timing Requirements
6.12.3.5
RGMII Receive Data and Control Timing Requirements
6.12.3.6
RMII Transmit Clock Switching Characteristics
6.12.3.7
RMII Transmit Data and Control Switching Characteristics
6.12.3.8
RMII Receive Clock Timing Requirements
6.12.3.9
RMII Receive Data and Control Timing Requirements
6.12.3.10
MII Transmit Switching Characteristics
6.12.3.11
MII Receive Clock Timing Requirements
6.12.3.12
MII Receive Timing Requirements
6.12.3.13
MII Transmit Clock Timing Requirements
6.12.3.14
MDIO Interface Timings
6.12.4
LVDS/Aurora Instrumentation and Measurement Peripheral
6.12.4.1
LVDS Interface Configuration
6.12.4.2
LVDS Interface Timings
6.12.5
UART Peripheral
6.12.5.1
SCI Timing Requirements
6.12.6
Inter-Integrated Circuit Interface (I2C)
6.12.6.1
I2C Timing Requirements #GUID-437677C7-D935-4733-A64D-553EFECA73F7/T4362547-185
6.12.7
Controller Area Network - Flexible Data-rate (CAN-FD)
6.12.7.1
Dynamic Characteristics for the CAN-FD TX and RX Pins
6.12.8
CSI2 Receiver Peripheral
6.12.8.1
CSI2 Switching Characteristics
6.12.9
Enhanced Pulse-Width Modulator (ePWM)
6.12.10
General-Purpose Input/Output
6.12.10.1
Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-45 #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-50
6.13
Emulation and Debug
6.13.1
Emulation and Debug Description
6.13.2
JTAG Interface
6.13.2.1
Timing Requirements for IEEE 1149.1 JTAG
6.13.2.2
Switching Characteristics for IEEE 1149.1 JTAG
6.13.3
ETM Trace Interface
6.13.3.1
ETM TRACE Timing Requirements
6.13.3.2
ETM TRACE Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Subsystems
7.3.1
RF and Analog Subsystem
7.3.1.1
RF Clock Subsystem
7.3.1.2
Transmit Subsystem
7.3.1.3
Receive Subsystem
7.3.2
Processor Subsystem
7.4
Other Subsystems
7.4.1
Hardware Accelerator Subsystem
7.4.2
Security – Hardware Security Module
7.4.3
ADC Channels (Service) for User Application
8
Monitoring and Diagnostics
8.1
Monitoring and Diagnostic Mechanisms
9
Applications, Implementation, and Layout
9.1
Application Information
9.2
Short and Medium Range Radar
9.3
Reference Schematic
10
デバイスおよびドキュメントのサポート
10.1
Device Support
10.2
Device Nomenclature
10.3
Tools and Software
10.4
Documentation support
10.5
サポート・リソース
10.6
Trademarks
10.7
静電気放電に関する注意事項
10.8
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
6.12.3.7
RMII Transmit Data and Control Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII11
t
d(REF_CLK-TXD)
Delay time, REF_CLK high to selected transmit signals valid
2
14.2
ns
t
dd(REF_CLK-TXEN)
Figure 6-14
MAC Transmit Interface Timing, RMIIn Operation