JAJSUK8R January   1993  – May 2024 SN54LVC157A , SN74LVC157A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions, SN54LVC157A
    4. 4.4  Recommended Operating Conditions, SN74LVC157A
    5. 4.5  Thermal Information
    6. 4.6  Electrical Characteristics, SN54LVC157A
    7. 4.7  Electrical Characteristics, SN74LVC157A
    8. 4.8  Switching Characteristics, SN54LVC157A
    9. 4.9  Switching Characteristics, SN74LVC157A
    10. 4.10 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Links
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.2 Functional Block Diagram

SN54LVC157A SN74LVC157A Logic Diagram (Positive Logic)
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
Figure 6-1 Logic Diagram (Positive Logic)