JAJSUL8C November   1998  – May 2024 CD54AC273 , CD54ACT273 , CD74AC273 , CD74ACT273

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3  Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Prerequisite for Switching Function
    7. 4.7 Switching Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Pin Configuration and Functions

CD54AC273 CD74AC273 CD54ACT273 CD74ACT273 CD54AC273, CD54ACT273 (CDIP) CD74AC273, CD74ACT273 (PDIP, SOIC) Top View Figure 3-1 CD54AC273, CD54ACT273 (CDIP) CD74AC273, CD74ACT273 (PDIP, SOIC) Top View
Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
!MR 1 I Master reset, active low
Q0 2 O Output Q0
D0 3 I Input D0
D1 4 I Input D1
Q1 5 O Output Q1
Q2 6 O Output Q2
D2 7 I Input D2
D3 8 I Input D3
Q3 9 O Output Q3
GND 10 - Ground
CP 11 I Clock, rising edge triggered
Q4 12 O Output Q4
D4 13 I Input D4
D5 14 I Input D5
Q5 15 O Output Q5
Q6 16 O Output Q6
D6 17 I Input D6
D7 18 I Input D7
Q7 19 O Output Q7
VCC 20 - Supply
(1) I = input, O = output, I/O = input or output, G = ground, P = power.