JAJSUR2N
May 1999 – September 2024
SN74LV4052A
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Thermal Information: SN74LV4052A
5.4
Recommended Operating Conditions
5.5
Electrical Characteristics
5.6
Timing Characteristics VCC = 2.5 V ± 0.2 V
5.7
Timing Characteristics VCC = 3.3 V ± 0.3 V
5.8
Timing Characteristics VCC = 5 V ± 0.5 V
5.9
AC Characteristics
5.10
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
6
Parameter Measurement Information
Figure 6-1
ON-State Resistance Test Circuit
Figure 6-2
OFF-State Switch Leakage-Current Test Circuit
Figure 6-3
ON-State Switch Leakage-Current Test Circuit
Figure 6-4
Propagation Delay Time, Signal Input to Signal Output
Figure 6-5
Switching Time (t
PZL
, t
PLZ
, t
PZH
, t
PHZ
), Control to Signal Output
Figure 6-6
Frequency Response (Switch ON)
Figure 6-7
Crosstalk Between Any Two Switches
Figure 6-8
Crosstalk Between Control Input and Switch Output
Figure 6-9
Feedthrough Attenuation (Switch OFF)
Figure 6-10
Sine-Wave Distortion