JAJSUR3J May   1999  – June 2024 SN74LV4051A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information: SN74LV4051A
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Characteristics VCC = 2.5V ± 0.2V
    7. 5.7  Timing Characteristics VCC = 3.3V ± 0.3V
    8. 5.8  Timing Characteristics VCC = 5V ± 0.5V
    9. 5.9  AC Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

SN74LV4051A D, PW Package, 16-Pin SOIC, TSSOP (Top View)Figure 4-1 D, PW Package, 16-Pin SOIC, TSSOP (Top View)
SN74LV4051A RGY Package 16-Pin VQFN With Exposed Thermal Pad (Top View)Figure 4-2 RGY Package 16-Pin VQFN With Exposed Thermal Pad (Top View)
Table 4-1 Pin Functions
PIN TYPE(2) DESCRIPTION
NAME NO.
A 11 I Selector line A for outputs (see Section 7.4 for specific information)
B 10 I Selector line B for outputs (see Section 7.4 for specific information)
C 9 I Selector line C for outputs (see Section 7.4 for specific information)
COM 3 O/I(1) Output/Input of mux
GND 7, 8 — Ground
INH 6 I(1) Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn them off.
Y0 13 I/O(1) Input/Output to mux
Y1 14 I/O(1) Input/Output to mux
Y2 15 I/O(1) Input/Output to mux
Y3 12 I/O(1) Input/Output to mux
Y4 1 I/O(1) Input/Output of mux
Y5 5 I/O(1) Input/Output to mux
Y6 2 I/O(1) Input/Output to mux
Y7 4 I/O(1) Input/Output to mux
VCC 16 — Device power
(1) These I/O descriptions represent the device when used as a multiplexer, when this device is operated as a demultiplexer pins Y0-Y7 may be considered outputs (O) and the COM pin may be considered inputs (I).
(2) I = inputs, O = outputs