JAJSUS7 June   2024 TLV9304-Q1

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Quad Channel
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Phase Reversal Protection
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Capacitive Load and Stability
      6. 6.3.6 Common-Mode Voltage Range
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 High Voltage Precision Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

For VS = (V+) – (V–) = 4.5V to 40V (±2.25V to ±20V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.5 ±2.5 mV
TA = –40°C to 125°C ±2.75
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±2 µV/℃
PSRR Input offset voltage versus power supply VCM = V– TA = –40°C to 125°C ±2 ±5 µV/V
Channel separation f = 0Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±10 pA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz   6 µVPP
  1   µVRMS
eN Input voltage noise density f = 1kHz 33   nV/√Hz
f = 10kHz   30  
iN Input current noise f = 1kHz   5   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.2 (V+) – 2 V
CMRR Common-mode rejection ratio VS = 40V, (V–) – 0.1V < VCM < (V+) – 2V TA = –40°C to 125°C 95 110 dB
VS = 4.5V, (V–) – 0.1V < VCM < (V+) – 2V 90
(V+) – 2V < VCM < (V+) + 0.1V See Common-Mode Voltage Range
INPUT CAPACITANCE
ZID Differential 110 || 4 MΩ || pF
ZICM Common-mode 6 || 1.5 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40V, VCM = V–
(V–) + 0.1V < VO < (V+) –  0.1V		 120 130 dB
TA = –40°C to 125°C 116 127
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1 MHz
SR Slew rate VS = 40V, G = +1, CL = 20 pF 3 V/µs
tS Settling time To 0.1%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 5 µs
To 0.1%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 2.5
To 0.01%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 6
To 0.01%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 3.5
Phase margin G = +1, RL = 10kΩ, CL = 20pF 60 °
Overload recovery time VIN  × gain > VS 1 µs
THD+N Total harmonic distortion + noise VS = 40V, VO = 1VRMS, G = -1, f = 1kHz 0.003%
OUTPUT
  Voltage output swing from rail Positive and negative rail headroom VS = 40V, RL = no load   3 mV
VS = 40V, RL = 10kΩ   50 75
VS = 40V, RL = 2kΩ   250 350
VS = 4.5V, RL = no load   1
VS = 4.5V, RL = 10kΩ   20 30
VS = 4.5V, RL = 2kΩ   40 75
ISC Short-circuit current ±60 mA
CLOAD Capacitive load drive See Typical Characteristics
ZO Open-loop output impedance f = 1MHz, IO = 0A 600 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0A 150 175 µA
TA = –40°C to 125°C 175