JAJSUT1B June   2024  – November 2024 TUSB2E221

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parametric Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 2.0
      2. 8.3.2 eUSB2
      3. 8.3.3 Cross MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power-Down Mode
      3. 8.4.3  UART Mode
      4. 8.4.4  Auto-Resume ECR
      5. 8.4.5  L2 State Interrupt Modes
      6. 8.4.6  Attach Detect Interrupt Mode
      7. 8.4.7  GPIO Mode
        1. 8.4.7.1 EQ0 as GPIO0
        2. 8.4.7.2 EQ1 as GPIO1
        3. 8.4.7.3 EQ2/INT as GPIO2
      8. 8.4.8  CROSS
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Target Interface
      2. 8.5.2 Register Access Protocol (RAP)
  10. 9 Register Map
    1. 9.1 TUSB2E221 Registers
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Dual Port System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 eUSB PHY Settings Recommendation
      3. 10.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Up Reset
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Example Layout
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PWC_1_1V8 Absolute worst case power consumption - One Repeater (VDD1V8 only)  VIOSEL is high or low, I2C interface active,  GPIOs in output mode, one repeater is disable and one repeater in HS mode with USB transmitting, maximum RX EQ, TX VOD and PE settings, maximum transition density. 275 mW
PWC_1_3V3 Absolute worst case power consumption - One Repeater (VDD3V3 only)  VIOSEL is high or low, I2C interface active,  GPIOs in output mode, one repeater is disable and one repeater in HS mode with USB transmitting, maximum RX EQ, TX VOD and PE settings, maximum transition density. 25 mW
PWC_2_1V8 Absolute worst case power consumption - Two Repeaters  (VDD1V8 only) VIOSEL is high or low, I2C interface active,  GPIOs in output mode, both repeaters in HS mode with USB transmitting, maximum RX EQ, TX VOD and PE settings, maximum transition density. 550 mW
PWC_2_3V3 Absolute worst case power consumption - Two Repeaters  (VDD3V3 only) VIOSEL is high or low, I2C interface active,  GPIOs in output mode, both repeaters in HS mode with USB transmitting, maximum RX EQ,  TX VOD and PE settings, maximum transition density.  50 mW
PHS_IOC_1 USB Audio ISOC High -Speed - one repeater only Maximum TX Vod/Maximum TX PE for both USB and eUSB2. Averaged over 8ms and only 1uFrame with data packet. Toffthreshold = 1/32. Host Peripheral mode. Frame Based Low power mode enabled 70 mW
PHS_IDLE_LP_1 High Speed Idle (Host Mode) - one repeater L0.Idle. TA = 85℃. (Typical at 25℃). Default PHY tuning settings for eUSB2 and USB. Frame based and response based low power mode enabled 26 70 mW
PHS_IDLE_LP_1 High Speed Idle (Peripheral Mode) - one repeater L0.Idle. TA = 85℃. (Typical at 25℃). Default PHY tuning settings for eUSB2 and USB. Frame based low power mode disabled and response based low power mode enabled 108 200 mW
PPD Powered down  Device powered, RESETB=Low, TA=25℃, (DP/DN Voltage ≤ VDD3V3). 10 µW
PDisabled Disabled Device powered, I2C/GPIO interfaces functional but idle, both repeaters are disabled put into their lowest power state and non-functional. TA=25℃, (DP/DN Voltage ≤ VDD3V3). 100 µW
PDetach_1 USB unconnected - One Repeater  I2C/GPIO interfaces idle, one repeater is disabled and one repeater is connected to a eUSB PHY and waiting for a USB attach event. TA = 25℃, (DP/DN Voltage ≤ VDD3V3) 100 µW
PDetach_2 USB unconnected - Two Repeater I2C/GPIO interfaces idle, both repeaters connected to a eUSB PHY and waiting for a USB attach event. TA = 25℃, (DP/DN Voltage ≤ VDD3V3) 150 µW
PSuspend_2 L2 Suspend I2C/GPIO interfaces idle, USB link is in L2, both repeaters monitoring for a resume/remote wake event. TA = 25℃, (DP/DN Voltage ≤ VDD3V3) 150 µW
PSleep_2 L1 Sleep Psleep_2  I2C/GPIO interfaces idle, both repeaters are supporting a USB connection, USB link is in L1, both repeaters monitoring for a L1 exit event. TA = 25℃, (DP/DN Voltage ≤ VDD3V3)  6 mW
PLS_Active_1 Low Speed Active - One Repeater I2C/GPIO interfaces idle, one repeater is disabled, other repeater in LS mode, maximum transition density. TA = 85℃. 52 mW
PFS_Active_1 Full Speed Active - One Repeater I2C/GPIO interfaces idle, one repeater is disabled, one repeater in FS mode, maximum transition density. TA = 85℃. 52 mW
PFS_Active_2 Full Speed Active - Two Repeater I2C/GPIO interfaces idle, Both repeaters in FS mode, maximum transition density. TA = 85℃. 68 mW
DIGITAL INPUTS
VIH High level input voltage CROSS, EQ0, EQ1 (1.2V input mode, VIOSEL=VSS) 0.702 V
VIH High level input voltage CROSS, EQ0, EQ1 (1.8V input mode, VIOSEL=VDD1V8) 1.053 V
VIL Low-level input voltage CROSS, EQ0, EQ1 (1.2V input mode, VIOSEL=VSS) 0.462 V
VIL Low-level input voltage CROSS, EQ0, EQ1 (1.8V input mode, VIOSEL=VDD1V8) 0.693 V
VIL Low-level input voltage VIOSEL (1.8V input) 0.613 V
VIH High level input voltage VIOSEL (1.8V input) 1.053 V
VIL Low-level input voltage RESETB (1.2V or 1.8V input mode) 0.35 V
VIH High level input voltage RESETB (1.2V or 1.8V input mode) 0.75 V
IIH High level input current VIH = 1.98V, VDD3V3=3.0V or 0V, VDD1V8=1.62V or 0V
CROSS, RESETB, EQ0, EQ1		 0.5 µA
IIL Low level input current VIL = 0V, VDD3V3=3.0V or 0V, VDD1V8=1.62V or 0V
CROSS, RESETB, EQ0, EQ1		 0.5 µA
DIGITAL OUTPUTS
VOH High level output voltage  EQ0, EQ11, EQ2/INT, push-pull I/O mode (IOH = 20µA and maximum 3pF Cload) (1.2V output mode) 0.81 V
VOH High level output voltage  EQ0, EQ1, EQ2/INT, push-pull I/O mode (IOH = 20µA and maximum 3pF Cload)(1.8V output mode) 1.21 V
VOL Low level output voltage EQ0, EQ1, EQ2/INT, push-pull I/O mode (IOL = 1mA) (1.2V output mode) 0.25 V
VOL Low level output voltage EQ0, EQ1, EQ2/INT, push-pull I/O mode (IOL = 1mA) (1.8V output mode) 0.35 V
IOL_PP Low level output current in push-pull mode
EQ0, EQ1, EQ2/INT (1.2V mode) VIOSEL=GND, VOL=0.4		 2.5 4 6 mA
IOL_PP Low level output current in push-pull mode
EQ0, EQ1, EQ2/INT (1.8V mode) VIOSEL=VDD1V8, VOL=0.4		 4 6 8 mA
IOH_PP High level output current in push-pull mode EQ0, EQ1, EQ2/INT, push-pull I/O mode (1.2V output mode) VIOSEL=GND 22 µA
IOH_PP High level output current in push-pull mode EQ0, EQ1, EQ2/INT, push-pull I/O mode (1.8V output mode)  VIOSEL=VDD1V8 50 µA
IOL Output current in open-drain mode EQ0, EQ1, EQ2/INT, VOL=0.4V, VIOSEL=VDD1V8, 1.8V mode 4 10 16 mA
IOL Output current in open-drain mode EQ0, EQ1, EQ2/INT, VOL=0.4V, VIOSEL=GND, 1.2V mode 4 9.2 16 mA
I2C (SDA, SCL)
VIL Low level input voltage, VIOSEL=VSS  SDA, SCL, V_I2C_Pullup = 1.08V to 1.32V 0.387 V
VIL Low level input voltage, VIOSEL=VDD1V8 SDA, SCL, V_I2C_Pullup = 1.62V to 1.96V 0.588 V
VIH High level output voltage, VIOSEL=VSS SDA, SCL, V_I2C_Pullup = 1.08V to 1.32V 0.833 V
VIH High level output voltage, VIOSEL=VDD1V8 SDA, SCL, V_I2C_Pullup = 1.62V to 1.98V 1.372 V
VHYS Input hysteresis, VIOSEL=VSS V_I2C_Pullup = 1.08V to 1.32V 0.020 V
VHYS Input hysteresis, VIOSEL=VDD1V8 V_I2C_Pullup = 1.62V to 1.98V 0.098 V
IIH High level input leakage current VIH = 1.98V 0.5 µA
IIL Low level input leakage current VIL = 0V 0.5 µA
IOL Open-drain drive strength VOL = 0.4V, VIOSEL = VDD1V8, 1.8V mode 8 10 12.6 mA
IOL Open-drain drive strength VOL = 0.4V, VIOSEL= GND, 1.2V mode 6.8 9 11.9 mA
USBA (DPA, DNA), USBB (DPB, DNB)
Zinp_Dx Impedance to GND, no pull up/down Vin=3.6V, VDD3V3=3.0V USB 2.0 Spec Section 7.1.6 (1) 390 kΩ
CIO_Dx Capacitance to GND Measured with VNA at 240MHz, Driver Hi-Z 10 pF
RPUI Bus pull-up resistor on upstream facing port (idle) USB 2.0 Spec Section 7.1.5 (1) 0.92 1.1 1.475 kΩ
RPUR Bus pull-up resistor on upstream facing port (receiving) USB 2.0 Spec Section 7.1.5 (1) 1.525 2.2 2.99 kΩ
RPD Bus pull-down resistor on downstream facing port USB 2.0 Spec Section 7.1.5 (1) 14.35 19 24.6 kΩ
VHSTERM Termination voltage in high speed USB 2.0 Spec Section 7.1.6.2 (1), The output voltage in the high-speed idle state –10 10 mV
USB TERMINATION
ZHSTERM_P Driver output resistance (which also serves as high speed termination) (VOH= 0 to 600mV) USB 2.0 Spec Section 7.1.1.1 (1), Default, U_HS_TERM_Px Setting 01 40.6 45 49.4 Ω
ZHSTERM_N Driver output resistance (which also serves as high speed termination) (VOH= 0 to 600mV) USB 2.0 Spec Section 7.1.1.1 (1), Default, U_HS_TERM_Px Setting 01 40.6 45 49.4 Ω
USBA, USBB INPUT LEVELS LS/FS
VIH High (driven) USB 2.0 Spec Section 7.1.4 (1) (measured at connector) 2 V
VIHZ High (floating) USB 2.0 Spec Section 7.1.4 (1) (HOST downstream port pull down resistor enabled and external device pull up 1.5kΩ +/-5% to 3.0V to 3.6V). 2.7 3.6 V
VIL Low USB 2.0 Spec  Section 7.1.4 (1) 0.8 V
VDI Differential input sensitivity (hysteresis is off) |(D+)-(D-)|; USB 2.0 Spec Figure 7-19 (1); (measured at connector) VCM=0.8V to 2.0V 0.2 V
USBA, USBB OUTPUT LEVELS LS/FS
VOL Low USB 2.0 Spec  Section 7.1.1 (1),  (measured at connector with RL of 1.425kΩ to 3.6V. ) 0 0.3 V
VOH High (Driven) USB 2.0 Spec Section 7.1.1 (1) (measured at connector with RL of 14.25kΩ to GND. ) 2.8 3.6 V
ZFSTERM Driver series output resistance USB 2.0 Spec Section 7.1.1 (1), Measured it during VOL or VOH 28 46 Ω
VCRS2 Output signal crossover voltage Measured as in USB 2.0 Spec Section 7.1.1 Figure 7-8 (1); Excluding the first transition from the Idle state. With external 1.5kΩ pullup on DP to 3.0V 1.3 2 V
VCRS Output signal crossover voltage Measured as in USB 2.0 Spec Section 7.1.1 Figure 7-8 (1); Excluding the first transition from the Idle state 1.3 2 V
USBA, USBB INPUT LEVELS HS
VHSSQ High-speed squelch/no-squelch detection threshold  USB 2.0 Spec Section 7.1.7.2 (specification refers to peak differential signal amplitude) (1), measured at 240MHz with increasing amplitude,
U_SQUELCH_THRESHOLD_Px Setting 100, VCM = –50mV to 500mV		 104 126 150 mV
VHSDSC High speed disconnect detection threshold USB 2.0 Spec Section 7.1.7.2 (specification refers to differential signal amplitude) (1). (+22.4%),
U_DISCONNECT_THRESHOLD_Px Setting 0111, VCM = 367mV to 770mV		 697 732 760 mV
EQ_UHS USB high-speed data receiver equalization, (measured indirectly through jitter) 240MHz, U_EQ_Px Setting 010 0.62 1.09 1.57 dB
USBA, USBB OUTPUT LEVELS HS
VHSOD High-speed data signaling swing Measured p-p, 10%, U_HS_TX_AMPLITUDE_Px Setting 0111, PE disabled,Test load is an ideal 45ohm to GND on DP and DN.  792 880 968 mV
VHSOL High-speed data signaling low, driver is off termination is on (measured single ended) USB 2.0 Spec Section 7.1.7.2 (1), PE disabled, Test load is an ideal 45Ω to GND on DP and DN.  –10 10 mV
VCHIRPJ Host/ Hub Chirp J level (differential voltage)  USB 2.0 Spec Section 7.1.7.2 (1) (PE is disabled. Swing setting has no impact but slew rate control has impact), Test load is an ideal 1.5kΩ pullup on DP. 700 900 1100 mV
VCHIRPK Device Chirp K level (differential voltage) USB 2.0 Spec Section 7.1.7.2 (1) (PE is disabled. Swing setting has no impact but slew rate control has impact), Test load is an ideal 45Ω to GND on DP and DN.  –900 –760 –500 mV
VCHIRPK Host/Hub Chirp K level (differential voltage) USB 2.0 Spec Section 7.1.7.2 (1) (PE is disabled. Swing setting has no impact but slew rate control has impact), Test load is an ideal 1.5kΩ pullup on DP. –900 –700 –500 mV
U2_TXPE High-speed TX Pre-emphasis U_HS_TX_PRE_EMPHASIS_Px Setting 001,Test load is an ideal 45Ω to GND on DP and DN.  0.62 0.9 1.2 dB
U2_TXPE_UI High-speed TX Pre-emphasis  U_HS_TX_PE_WIDTH_Px Setting 00 (measured with PE=2.5dB setting of 101), Test load is an ideal 45Ω to GND on DP and DN.  0.25 0.35 0.41 UI
U2_TXPE_UI High-speed TX Pre-emphasis width U_HS_TX_PE_WIDTH_Px Setting 01 (measured with PE=2.5dB setting of 101), Test load is an ideal 45Ω to GND on DP and DN.  0.35 0.45 0.55 UI
U2_TXPE_UI High-speed TX Pre-emphasis width U_HS_TX_PE_WIDTH_Px Setting 10 (measured with PE=2.5dB setting of 101), Test load is an ideal 45Ω to GND on DP and DN.  0.44 0.55 0.67 UI
U2_TXPE_UI High-speed TX Pre-emphasis width U_HS_TX_PE_WIDTH_Px Setting 11 (measured with PE=2.5dB setting of 101), Test load is an ideal 45Ω to GND on DP and DN.  0.54 0.65 0.77 UI
U2_TXCM High-speed TX DC Common Mode All Swing settings with PE disabled 100 200 300 mV
eUSB2 TERMINATION
RSRC_HS High-speed transmit source termination impedance eUSB2 Spec Section 7.1.1 (2) 33 40 47 Ω
ΔRSRC_HS High-speed source impedance mismatch eUSB2 Spec Section 7.1.1 (2) 4 Ω
RRCV_DIF High-speed differential receiver termination (repeater) eUSB2 Spec Section 7.1.2 (2) 74 80 86 Ω
RPD Pulldown resistors on eDP/eDN eUSB2 Spec Section 7.3 (2), active during LS, FS and HS  6 8 10 kΩ
RSRC_LSFS Transmit output impedance eUSB2 Spec Section 7.2.1 (2), Table 7-13 TX output impedance to match spec version 1.10 28 44 59 Ω
CIO_eDx Differential capacitance  Measured with VNA at 240MHz, Driver Hi-Z (VCM = 120mV to 450mV), Measured differentially. 3.7 5 pF
eUSB0, eUSB1 FS/LS INPUT LEVELS
VIL Single-ended input low eUSB2 Spec Section 7.2.1, Table 7-13 (2) –0.1 0.399 V
VIH Single-ended input high eUSB2 Spec Section 7.2.1, Table 7-13 (2) 0.819 1.386 V
VHYS Receive single-ended hysteresis voltage eUSB2 Spec Section 7.2.1, Table 7-13 (2) 43.2 mV
eUSB0, eUSB1 FS/LS OUTPUT LEVELS
VOL Single-ended output low eUSB2 Spec Section 7.2.1, Table 7-13 (2) 0.1 V
VOH Single-ended output high eUSB2 Spec Section 7.2.1, Table 7-13 (2) 0.918 1.32 V
eUSB0, eUSB1 HS INPUT LEVELS
VCM_RX_AC Receiver AC common mode (50MHz-480MHz) eUSB2 Spec Section 7.1.2 (informative) (2), across the DC common mode range of 120mV to 280mV. (RX capability tested with intentional TX Rise/Fall Time mismatch and prop delay mismatch) –60 60 mV
CRX_CM Receive center-tapped capacitance eUSB2 Spec Section 7.1.2 (informative) (2) 15 50 pF
VEHSSQ Squelch/No-squelch detect threshold  eUSB2 Spec Section 7.1.2 (2), (measured as differential peak voltage at 240MHz with increasing amplitude), VCM = 120mV to 450mV 47 66 83 mV
EQ_EHS eUSB2 High-speed data receiver equalization, (measured indirectly through jitter) 240MHz E_EQ_P1x Setting 0010 0.59 1.12 1.4 dB
eUSB0, eUSB1 HS OUTPUT LEVELS
VEHSOD Transmit differential (terminated) Measured p2p, RL = 80Ω, E_HS_TX_AMPLITUDE_ Px setting 100, ideal 80Ω Rx differential termination load 396 440 484 mV
E_TXPE High-speed TX Pre-emphasis E_HS_TX_PRE_EMPHASIS_Px Setting 010 1.01 1.29 1.57 dB
(1) USB 2.0 Promoter Group 2000, USB 2.0 Specification USB 2.0 Promoter Group
(2) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev. 1.2 USB Implementers Forum