JAJSUT1B June   2024  – November 2024 TUSB2E221

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Variants
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parametric Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 2.0
      2. 8.3.2 eUSB2
      3. 8.3.3 Cross MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1  Repeater Mode
      2. 8.4.2  Power-Down Mode
      3. 8.4.3  UART Mode
      4. 8.4.4  Auto-Resume ECR
      5. 8.4.5  L2 State Interrupt Modes
      6. 8.4.6  Attach Detect Interrupt Mode
      7. 8.4.7  GPIO Mode
        1. 8.4.7.1 EQ0 as GPIO0
        2. 8.4.7.2 EQ1 as GPIO1
        3. 8.4.7.3 EQ2/INT as GPIO2
      8. 8.4.8  CROSS
      9. 8.4.9  USB 2.0 High-Speed HOST Disconnect Detection
      10. 8.4.10 Frame Based Low Power Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Target Interface
      2. 8.5.2 Register Access Protocol (RAP)
  10. 9 Register Map
    1. 9.1 TUSB2E221 Registers
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Dual Port System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 eUSB PHY Settings Recommendation
      3. 10.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Up Reset
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Example Layout
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.7 Timing Requirements

MIN NOM MAX UNIT
I/O TIMING
t_GPIO_PW Minimum GPIO pulse width for INT event 8 µs
RESET TIMING
t_VDD1V8_RAMP Ramp time for VDD1V8 to reach minimum 1.62V 2 ms
t_VDD3V3_RAMP Ramp time for VDD3V3 to reach minimum 3.0V 2 ms
t_su_CROSS Setup time for CROSS sampled at the deassertion of RESETB 0 ms
t_hd_CROSS Hold time for CROSS sampled at the deassertion of RESETB 3 ms
t_aRESETB Duration for RESETB to be asserted low to complete reset while powered 10 µs
t_RH_READY Time for device to be ready to accept RAP and I2C requests and eUSB2 interface to be ready after RESETB is deasserted or (VDD1V8 and VDD3V3) reach minimum recommended voltages, whichever is later  3 ms
t_RS_READY Time for device to be ready to accept RAP and I2C requests and eUSB2 interface to be ready after soft reset through I2C 350 µs
REPEATER TIMING
TJ1E Total additive jitter for eUSB2 to USB 2.0 (output jitter - input jitter) of repeater when one of the two repeater is disabled. (must also include all complete SOP bits and measured with eUSB2 TX rise/fall time skew and intra-pair prop delay skew, refer to VCM_RX_AC) [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel]. Egress setup diagram   25 42 ps
TJ1I Total additive jitter for USB to eUSB2 (output jitter - input jitter) of repeater when one of the two repeater is disabled. [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel]. Ingress setup diagram  25 42 ps
TJ2E Total additive jitter for eUSB2 to USB (output jitter - input jitter) of repeater when both repeaters are active. [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel] 60 ps
TJ2I Total additive jitter for USB to eUSB2 (output jitter - input jitter) of repeater when both repeaters are active. [RX EQ disabled, TX PE disabled, VOD nominal setting and no input or output channel] 60 ps

Te_to_U_DJ1		 eUSB2 to USB 2.0 repeater FS jitter to next transition (Per eUSB2 spec 1.1 Table 7-13 Note 1 & 2 condition for Supply and GND delta (1)) 
–6.0
+6.0		 ns

TU_to_e_DJ1		 USB 2.0 to eUSB2 repeater FS jitter to next transition (Per eUSB2 spec 1.1 Table 7-13 Note1 & 2 condition for Supply and GND delta (1))  
–3.0
+3.0		 ns

TDJ2_e2U		 Repeater FS paired transition jitter in eUSB2 to USB 2.0 direction (Relaxed relative to THDJ2 defined by USB 2.0 +/-1ns) 
–1.5
+1.5		 ns

TDJ2_U2e		 Repeater FS paired transition jitter in USB 2.0 to eUSB2 direction (Relaxed relative to THDJ2 defined by USB 2.0 +/-1ns) 
–1.5
+1.5		 ns
MODE TIMING
TMODE_SWITCH Time needed to change mode from UART bypass mode to and from USB mode 1 µs
TUART_START Time needed to start transmitting UART data after entering UART bypass mode 2 ms
I2C (FM+)
tSU_STA Start setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 260   ns
tSU_STO Stop setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 260     ns
tHD_STA Start hold time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 260 ns
tSU_DAT Data input or False start/stop, setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 50 ns
tHD_DAT Data input or False start/stop, hold time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 0 ns
tVD_DAT, tVD_ACK SDA output delay, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 20 450 ns
tHD_DAT_SL Data hold time when device is transmitting  6.67 ns
tSP Glitch width suppressed 50 91 ns
tBUF Bus free time between a STOP and START condition (host minimum spec that device must tolerate) 0.5 µs
tLOW Low Period for SCL clock (host minimum spec that device must tolerate) 0.5 µs
tHIGH High Period for SCL clock (host minimum spec that device must tolerate) 0.26 µs
I2C (FM)
tSU_STO Stop setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 600     ns
tHD_STA Start hold time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 600     ns
tSU_STA Start setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 600 ns
tSU_DAT Data input or False start/stop, setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 100 ns
tHD_DAT Data input or False start/stop, hold time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 0 ns
tVD_DAT, tVD_ACK SDA output delay, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 20 900 ns
tHD_DAT_SL Data hold time when device is transmitting 13.5 ns
tSP Glitch width suppressed 50 91 ns
tBUF Bus free time between a STOP and START condition  (host minimum spec that device must tolerate) 1.3 µs
tLOW Low Period for SCL clock  (host minimum spec that device must tolerate) 1.3 µs
tHIGH High Period for SCL clock (host minimum spec that device must tolerate) 0.6 µs
I2C (STD)
tSU_STO Stop setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 4     µs
tHD_STA Start hold time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 4     µs
tSU_STA Start setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 4.7 µs
tSU_DAT Data input or False start/stop, setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 250 ns
tHD_DAT Data input or False start/stop, hold time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 5 µs
tVD_DAT, tVD_ACK SDA output delay, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 3.45 µs
tHD_DAT_SL Data hold time when device is transmitting 13.5 ns
tSP Glitch width suppressed 50 91 ns
tBUF Bus free time between a STOP and START condition (host minimum spec that device must tolerate) 4.7 µs
tLOW Low Period for SCL clock (host minimum spec that device must tolerate) 4.7 µs
tHIGH High Period for SCL clock (host minimum spec that device must tolerate) 4.0 µs
(1) USB Implementers Forum (2018). Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Rev. 1.2 USB Implementers Forum