JAJSUX5 June   2024 TMUX1308A-Q1 , TMUX1309A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information: TMUX1308A-Q1
    4. 6.4  Thermal Information: TMUX1309A-Q1
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Logic and Dynamic Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Injection Current Coupling
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 Injection Current Control
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 High-Impedance Optimization
      6. 8.3.6 Injection Current Control
        1. 8.3.6.1 TMUX13xxA-Q1 is Powered, Channel is Unselected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        2. 8.3.6.2 TMUX13xxA-Q1 is Powered, Channel is Selected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        3. 8.3.6.3 TMUX13xxA-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0V, VINPUT = 3V)
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Short To Battery Protection
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

5 Pin Configuration and Functions

TMUX1308A-Q1 TMUX1309A-Q1 TMUX1308A-Q1: PW Package,16-Pin TSSOP(Top View)Figure 5-1 TMUX1308A-Q1: PW Package,16-Pin TSSOP(Top View)
Table 5-1 Pin Functions TMUX1308A-Q1
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S4 1 I/O Source pin 4. Signal path can be an input or output.
S6 2 I/O Source pin 6. Signal path can be an input or output.
D 3 I/O Drain pin (common). Signal path can be an input or output.
S7 4 I/O Source pin 7. Signal path can be an input or output.
S5 5 I/O Source pin 5. Signal path can be an input or output.
EN 6 I Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[2:0] address inputs determine which switch is turned on as listed in Section 8.5.
N.C. 7 Not Connected Not internally connected.
GND 8 P Ground (0V) reference
A2 9 I Address line 2. Controls the switch configuration as listed in Section 8.5.
A1 10 I Address line 1. Controls the switch configuration as listed in Section 8.5.
A0 11 I Address line 0. Controls the switch configuration as listed in Section 8.5.
S3 12 I/O Source pin 3. Signal path can be an input or output.
S0 13 I/O Source pin 0. Signal path can be an input or output.
S1 14 I/O Source pin 1. Signal path can be an input or output.
S2 15 I/O Source pin 2. Signal path can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
Thermal pad — Exposed thermal pad with conductive die attached. No requirement to solder this pad. If connected, then it should be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 8.4.
TMUX1308A-Q1 TMUX1309A-Q1 TMUX1309A-Q1: PW Package,16-Pin TSSOP(Top View)Figure 5-2 TMUX1309A-Q1: PW Package,16-Pin TSSOP(Top View)
Table 5-2 Pin Functions TMUX1309A-Q1
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S0B 1 I/O Source pin 0 of mux B. Can be an input or output.
S2B 2 I/O Source pin 2 of mux B. Can be an input or output.
DB 3 I/O Drain pin (Common) of mux B. Can be an input or output.
S3B 4 I/O Source pin 3 of mux B. Can be an input or output.
S1B 5 I/O Source pin 1 of mux B. Can be an input or output.
EN 6 I Active low logic input. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on.
N.C. 7 Not Connected Not internally connected.
GND 8 P Ground (0V) reference
A1 9 I Address line 1. Controls the switch configuration as listed in Section 8.5.
A0 10 I Address line 0. Controls the switch configuration as listed in Section 8.5.
S3A 11 I/O Source pin 3 of mux A. Can be an input or output.
S0A 12 I/O Source pin 0 of mux A. Can be an input or output.
DA 13 I/O Drain pin (Common) of mux A. Can be an input or output.
S1A 14 I/O Source pin 1 of mux A. Can be an input or output.
S2A 15 I/O Source pin 2 of mux A. Can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
Thermal pad — Exposed thermal pad with conductive die attached. No requirement to solder this pad. If connected, then it should be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 8.4.