JAJSUX5 June   2024 TMUX1308A-Q1 , TMUX1309A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information: TMUX1308A-Q1
    4. 6.4  Thermal Information: TMUX1309A-Q1
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Logic and Dynamic Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Injection Current Coupling
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 Injection Current Control
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 High-Impedance Optimization
      6. 8.3.6 Injection Current Control
        1. 8.3.6.1 TMUX13xxA-Q1 is Powered, Channel is Unselected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        2. 8.3.6.2 TMUX13xxA-Q1 is Powered, Channel is Selected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        3. 8.3.6.3 TMUX13xxA-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0V, VINPUT = 3V)
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Short To Battery Protection
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

8.3.4 Fail-Safe Logic

The TMUX1308A-Q1 and TMUX1309A-Q1 device have Fail-Safe Logic on the control input pins (EN, A0, A1, and A2) allowing for operation up to 5.5V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the select pins of the TMUX1308A-Q1 and TMUX1309A-Q1 to be ramped to 5.5V while VDD = 0V. Additionally, the feature enables operation of the multiplexers with VDD = 1.8V while allowing the select pins to interface with a logic level of another device up to 5.5V, eliminating the potential need for an external voltage translator.