JAJSV10H December   2009  – July 2024 DRV8412

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Package Heat Dissipation Ratings
    6. 5.6 Package Power Deratings (DRV8412) #GUID-2A6DB468-D895-404F-A2E6-05A442AE2834/SLES2429141
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Error Reporting
      2. 6.3.2 Device Protection System
        1. 6.3.2.1 Bootstrap Capacitor Undervoltage Protection
        2. 6.3.2.2 Overcurrent (OC) Protection
        3. 6.3.2.3 Overtemperature Protection
        4. 6.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
      3. 6.3.3 Device Reset
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Full Bridge Mode Operation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Motor Voltage
          2. 7.2.1.2.2 Current Requirement of 12V Power Supply
          3. 7.2.1.2.3 Voltage of Decoupling Capacitor
          4. 7.2.1.2.4 Overcurrent Threshold
          5. 7.2.1.2.5 Sense Resistor
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Parallel Full Bridge Mode Operation
      3. 7.2.3 Stepper Motor Operation
      4. 7.2.4 TEC Driver
      5. 7.2.5 LED Lighting Driver
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
      2. 7.3.2 Power Supplies
      3. 7.3.3 System Power-Up and Power-Down Sequence
        1. 7.3.3.1 Powering Up
        2. 7.3.3.2 Powering Down
      4. 7.3.4 System Design Recommendations
        1. 7.3.4.1 VREG Pin
        2. 7.3.4.2 VDD Pin
        3. 7.3.4.3 OTW Pin
        4. 7.3.4.4 Mode Select Pin
        5. 7.3.4.5 Parallel Mode Operation
        6. 7.3.4.6 TEC Driver Application
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Material Recommendation
        2. 7.4.1.2 Ground Plane
        3. 7.4.1.3 Decoupling Capacitor
        4. 7.4.1.4 AGND
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Current Shunt Resistor
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 DRV8412 Thermal Via Design Recommendation
  9. 7Device and Documentation Support
    1. 7.1 ドキュメントの更新通知を受け取る方法
    2. 7.2 サポート・リソース
    3. 7.3 Trademarks
    4. 7.4 静電気放電に関する注意事項
    5. 7.5 用語集
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

6.4 Device Functional Modes

The DRV841x2 supports four different modes of operation:

  1. Dual full bridges (FB) (two PWM inputs each full bridge) or four half bridges (HB) with CBC current limit
  2. Dual full bridges (two PWM inputs each full bridge) or four half bridges with OC latching shutdown (no CBC current limit)
  3. Parallel full bridge (PFB) with CBC current limit
  4. Dual full bridges (one PWM input each full bridge) with CBC current limit

In mode 1 and 2, PWM_A controls half bridge A, PWM_B controls half bridge B, and so forth Figure 7-1 shows an application example for full bridge mode operation.

In parallel full bridge mode (mode 3), PWM_A controls both half bridges A and B, and PWM_B controls both half bridges C and D, while PWM_C and PWM_D pins are not used (recommended to connect to ground). Bridges A and B are synchronized internally (even during CBC), and so are bridges C and D. OUT_A and OUT_B should be connected together and OUT_C and OUT_D should be connected together after the output inductor or ferrite bead. If RESET_AB or RESET_CD are low, all four outputs become high-impedance. Figure 7-8 shows an example of parallel full bridge mode connection.

In mode 4, one PWM signal controls one full bridge to relieve some I/O resource from MCU, that is, PWM_A controls half bridges A and B and PWM_C controls half bridges C and D. In this mode, the operation of half bridge B is complementary to half bridge A, and the operation of half bridge D is complementary to half bridge C. For example, when PWM_A is high, high side FET in half bridge A and low side FET in half bridge B will be on and low side FET in half bridge A and high side FET in half bridge B will be off. Since PWM_B and PWM_D pins are not used in this mode, it is recommended to connect them to ground.

In operation modes 1, 2, and 4 (CBC current limit is used), once the CBC current limit is hit, the driver will be deactivated until the next PWM cycle starts. However, in order for the output to be recovered, the PWM input corresponding to that driver in CBC must be toggled. Because of this, CBC mode does not support operation when one half-bridge PWM input is tied to dc logic level.

Because each half bridge has independent supply and ground pins, a shunt sensing resistor can be inserted between PVDD to PVDD_X or GND_X to GND (ground plane). A high side shunt resistor between PVDD and PVDD_X is recommended for differential current sensing because a high bias voltage on the low side sensing could affect device operation. If low side sensing has to be used, a shunt resistor value of 10 mΩ or less or sense voltage 100mV or less is recommended.

DRV8412 DRV8432 Cycle-by-Cycle Operation With High-Side OC
Dashed line: normal operation; solid line: CBC event
Figure 6-1 Cycle-by-Cycle Operation With High-Side OC
DRV8412 DRV8432 Cycle-by-Cycle Operation With Low-Side OC
Dashed line: normal operation; solid line: CBC event
Figure 6-2 Cycle-by-Cycle Operation With Low-Side OC