JAJSV60E November   1998  – August 2024 CD54AC74 , CD74AC74

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 概要
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Timing Requirements, VCC = 1.5 V
    7. 4.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 4.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 4.9  Switching Characteristics, VCC = 1.5 V
    10. 4.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 4.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 4.12 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1.     Power Supply Recommendations
    2. 7.1 Layout
      1. 7.1.1 Layout Guidelines
      2. 7.1.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.1 Overview

The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.