JAJSVF9 September   2024 TSD5402-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements for I2C Interface Signals
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input and Preamplifier
      2. 6.3.2 Pulse-Width Modulator (PWM)
      3. 6.3.3 Gate Drive
      4. 6.3.4 Power FETs
      5. 6.3.5 Load Diagnostics
        1. 6.3.5.1 Load Diagnostics Sequence
        2. 6.3.5.2 Faults During Load Diagnostics
      6. 6.3.6 Protection and Monitoring
      7. 6.3.7 I2C Serial Communication Bus
        1. 6.3.7.1 I2C Bus Protocol
        2. 6.3.7.2 Random Write
        3. 6.3.7.3 Random Read
        4. 6.3.7.4 Sequential Read
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Control Pins
      2. 6.4.2 EMI Considerations
      3. 6.4.3 Operating Modes and Faults
  8. 7 Register Maps
    1. 7.1 I2C Address Register Definitions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Amplifier Output Filtering
        2. 8.2.1.2 Amplifier Output Snubbers
        3. 8.2.1.3 Bootstrap Capacitors
        4. 8.2.1.4 Analog Signal Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Unused Pin Connections
          1. 8.2.2.1.1 HI-Z Pin
          2. 8.2.2.1.2 STANDBY Pin
          3. 8.2.2.1.3 I2C Pins (SDA and SCL)
          4. 8.2.2.1.4 Terminating Unused Outputs
          5. 8.2.2.1.5 Using a Single-Ended Signal Input
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
        1. 8.4.2.1 Top Layer
        2. 8.4.2.2 Second Layer – Signal Layer
        3. 8.4.2.3 Third Layer – Power Layer
        4. 8.4.2.4 Bottom Layer – Ground Layer
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
      1. 11.1.1 Packaging Information
      2. 11.1.2 Tape and Reel Information

5.3 Recommended Operating Conditions

MINNOMMAXUNIT
V(PVDD_OP)Supply voltage range relative to GND. Includes ac transients, requires proper decoupling.(3)4-Ω ±20% load (or higher)4.514.418V
2-Ω ±20% load514.418
V(PVDD_RIPPLE)Maximum ripple on PVDDV(PVDD) < 8 V1Vpp
V(HI-Z)HI-Z pin voltage range relative to GND-0.33.35.5V
V(AIN)(1)Analog input-signal levelAC-coupled input voltage00.25–1(2)Vrms
V(IH_STANDBY)HI-Z and STANDBY pins input voltage for logic-level high2V
V(IL_STANDBY)HI-Z and STANDBY pins input voltage for logic-level low0.7V
V(IH_SCL)SCL pin input voltage for logic-level highR(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V2.1V
V(IH_SDA)SDA pin input voltage for logic-level highR(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V2.1V
V(IL_SCL)SCL pin input voltage for logic-level lowR(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V1.1V
V(IL_SDA)SDA pin input voltage for logic-level lowR(PU_I2C) = 4.7-kΩ pullup, supply voltage = 3.3 V or 5 V1.1V
TAAmbient temperature–40125°C
R(L)Nominal load impedanceWhen using low-impedance loads, do not exceed overcurrent limit.24

60

Ω
V(PU)Pullup voltage supply (for open-drain logic outputs)V(PU) must be less than (V(PVDD) - 1V) during normal operation.33.35.5V
R(PU_EXT)External pullup resistor on open-drain logic outputsResistor connected between open-drain logic output and V(PU) supply.1050kΩ
R(PU_I2C)I2C pullup resistance on SDA and SCL pins14.710kΩ
C(PVDD)External capacitor on the PVDD pin, typical value ± 20%(3)10μF
C(BYP)External capacitor on the BYP pin, typical value ± 10%1μF
C(OUT)External capacitance to GND on OUT_X pins4μF
C(IN)External capacitance to analog input pin in series with input signal1μF
C(BSTN), C(BSTP)External boostrap capacitor, typical value ± 20%220nF
(1) Signal input for full unclipped output with gains of 36dB, 32dB, 26dB, and 20dB
(2) Maximum recommended input voltage is determined by the gain setting.
(3) See the section.