JAJSVI1 October   2024 TPS25763-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Components
    5. 6.5  Thermal Information
    6. 6.6  Buck-Boost Regulator
    7. 6.7  CC Cable Detection Parameters
    8. 6.8  CC VCONN Parameters
    9. 6.9  CC PHY Parameters
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 ADC Characteristics
    13. 6.13 TVSP Parameters
    14. 6.14 Input/Output (I/O) Characteristics
    15. 6.15 BC1.2 Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power Management and Supervisory Circuitry
        1. 8.3.1.1 VIN UVLO and Enable/UVLO
        2. 8.3.1.2 Internal LDO Regulators
      2. 8.3.2  TVSP Device Configuration and ESD Protection
      3. 8.3.3  External NFET and LSGD
      4. 8.3.4  Buck-Boost Regulator
        1. 8.3.4.1  Buck-Boost Regulator Operation
        2. 8.3.4.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 8.3.4.3  VIN Supply and VIN Over-Voltage Protection
        4. 8.3.4.4  Feedback Paths and Error Amplifiers
        5. 8.3.4.5  Transconductors and Compensation
        6. 8.3.4.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 8.3.4.7  VBUS Overvoltage Protection
        8. 8.3.4.8  VBUS Undervoltage Protection
        9. 8.3.4.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 8.3.4.10 Buck-Boost Peak Current Limits
      5. 8.3.5  USB-PD Physical Layer
        1. 8.3.5.1 USB-PD Encoding and Signaling
        2. 8.3.5.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.5.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.5.4 USB-PD BMC Transmitter
        5. 8.3.5.5 USB-PD BMC Receiver
        6. 8.3.5.6 Squelch Receiver
      6. 8.3.6  VCONN
      7. 8.3.7  Cable Plug and Orientation Detection
        1. 8.3.7.1 Configured as a Source
        2. 8.3.7.2 Configured as a Sink
        3. 8.3.7.3 Configured as a DRP
        4. 8.3.7.4 Overvoltage Protection (Px_CC1, Px_CC2)
      8. 8.3.8  ADC
        1. 8.3.8.1 ADC Divider Ratios
      9. 8.3.9  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      10. 8.3.10 DisplayPort Hot-Plug Detect (HPD)
      11. 8.3.11 USB2.0 Low-Speed Endpoint
      12. 8.3.12 Digital Interfaces
        1. 8.3.12.1 General GPIO
        2. 8.3.12.2 I2C Buffer
      13. 8.3.13 I2C Interface
        1. 8.3.13.1 I2C Interface Description
        2. 8.3.13.2 I2C Clock Stretching
        3. 8.3.13.3 I2C Address Setting
        4. 8.3.13.4 Unique Address Interface
        5. 8.3.13.5 I2C Pullup Resistor Calculation
      14. 8.3.14 Digital Core
        1. 8.3.14.1 Device Memory
        2. 8.3.14.2 Core Microprocessor
      15. 8.3.15 NTC Input
      16. 8.3.16 Thermal Sensors and Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application GUI Selections
        2. 9.2.2.2 EEPROM Selection
        3. 9.2.2.3 EN/UVLO
        4. 9.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 9.2.2.5 Inductor Currents
        6. 9.2.2.6 Output Capacitor
        7. 9.2.2.7 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     106

8.3.6 VCONN

Internal VCONN sourcing power paths are firmware configurable. Using only the internal LDO_5V supply, PortA is able to draw 20 mA continuously. If an external 5-V regulator is connected to the LDO_5V pin and the application GUI settings are enabled, PortA is able to draw 200 mA continuously. When disabled, blocking FETs in the PortA VCONN paths protect the LDO_5V rail from high-voltage and reverse current.

When VCONN power is enabled and provided, the internal VCONN power switches have a current limit of ILIMVC. If the VCONN load current exceeds ILIMVC, the current clamping circuit activates within tiOS_PP_CABLE and the switch behaves as a constant current source. Reverse current blocking is disabled when current is flowing to Px_CC1 or Px_CC2.

TPS25763-Q1 VCONN Power Switches Figure 8-27 VCONN Power Switches

When operating in current limit, the VCONN FET temperature rises. Local temperature sensors disable the Px_VCONN path in current limit when Tsensor > TSD_Px_VCONN within tPP_CABLE_off. The application firmware enters USB Type-C Error Recovery on the affected port.

LDO_5V must remain above its under voltage lock out threshold (VLDO_5V(UVLO_F)) for Px_VCONN operation. If the VLDO_5V(UVLO_F) threshold is reached, Px_VCONN paths are automatically disabled within tPP_CABLE_off.