JAJSVM2 November   2024 TDP142-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

4 Pin Configuration and Functions

TDP142-Q1 RGF Package40-Pin (VQFN)Top ViewFigure 4-1 RGF Package40-Pin (VQFN)Top View
Table 4-1 Pin Functions
PINI/ODESCRIPTION
NAMENO.
INDP0p1IDP Differential positive input for DisplayPort Lane 0.
INDP0n2IDP Differential negative input for DisplayPort Lane 0.
A034 Level IWhen I2C_EN = 0, leave the pin unconnected. When I2C_EN is not ‘0’, this pin also sets the TDP142-Q1 I2C address. See Table 6-4. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
INDP1p4Diff IDP Differential positive input for DisplayPort Lane 1.
INDP1n5Diff IDP Differential negative input for DisplayPort Lane 1.
DPEQ0/A164 Level IDisplayPort Receiver EQ control. This along with DPEQ1 selects the DisplayPort receiver equalization gain. Refer to Table 6-2 for equalization settings. When I2C_EN is not ‘0’, this pin also sets the TDP142-Q1 I2C address. See Table 6-4.
INDP2p7Diff IDP Differential positive input for DisplayPort Lane 2.
INDP2n8Diff IDP Differential negative input for DisplayPort Lane 2.
I2C_EN94 Level II2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled).
R = TI Test Mode (I2C enabled at 3.3V).
F = I2C enabled at 1.8V when RSVD11 = "0" and RSVD10 = "0". Otherwise, GPIO mode (I2C disabled)
1 = I2C enabled at 3.3 V.
INDP3p10Diff IDP Differential positive input for DisplayPort Lane 3.
INDP3n11Diff IDP Differential negative input for DisplayPort Lane 3.
VCC12, 20, 33, 38P3.3V Power Supply.
TEST1/SCL132 Level IWhen I2C_EN=’0’, pull down with 10k or directly connect to ground. Otherwise this pin is I2C clock. When used for I2C clock, pull up this pin to the VCC I2C supply of the I2C controller.
TEST2/SDA142 Level IWhen I2C_EN=’0’ , pull down with 10k or directly connect to ground. Otherwise this pin is I2C data. When used for I2C data, pull up this pin to the VCC I2C supply of the I2C controller.
DPEN/HPDIN152 Level I
(Failsafe)
(PD)		DP Enable Pin. When I2C_EN = ‘0’, this pin enables or disables the DisplayPort functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled. (Pull down with 10k resistor)
H = DisplayPort Enabled. (Pull up with 10k resistor)
When I2C_EN is not "0" this pin is an input for Hot Plug Detect (HPD) received from DisplayPort sink. When this HPDIN is low for greater than 2ms, all DisplayPort lanes are disabled.
AUXp16I/O, CMOSThis pin along with AUXN is used by the TDP142-Q1 for AUX snooping. See the Application and Implementation section for more detail.
AUXn17I/O, CMOSThis pin along with AUXP is used by the TDP142-Q1 for AUX snooping. See the Application and Implementation section for more detail.
RSVD618I/O, CMOSReserved.(1)
RSVD719I/O, CMOSReserved.(1)
SNOOPENZ/RSVD821(2)I/O
(PD)		When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0 , this pin is SNOOPENZ (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active).
OUTDP3p22Diff ODP Differential positive output for DisplayPort Lane 3.
OUTDP3n23Diff ODP Differential negative output for DisplayPort Lane 3.
HPDIN/RSVD924(2)I/O
(PD)		When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are disabled.
OUTDP2p25Diff ODP Differential positive output for DisplayPort Lane 2.
OUTDP2n26Diff ODP Differential negative output for DisplayPort Lane 2.
RSVD1027IReserved. Connect to GND when 1.8V I2C is used, otherwise leave pin floating.
OUTDP1n28Diff ODP Differential negative output for DisplayPort Lane 1.
OUTDP1p29Diff ODP Differential positive output for DisplayPort Lane 1.
RSVD1130IReserved. Connect to GND when 1.8V I2C is used, otherwise leave pin floating.
OUTDP0n31Diff ODP Differential negative output for DisplayPort Lane 0.
OUTDP0p32Diff ODP Differential positive output for DisplayPort Lane 0.
DPEQ1344 Level IDisplayPort Receiver EQ control. This along with DPEQ0 selects the DisplayPort receiver equalization gain. Refer to Table 6-2 for equalization settings.
RSVD135IReserved.(1)
RSVD236OReserved.(1)
RSVD337OReserved.(1)
RSVD439IReserved.(1)
RSVD540IReserved.(1)
(1) Leave unconnected on PCB.
(2) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.