JAJU299A June   2017  – January 2023

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TPS82130
    3. 2.3 Design Considerations
      1. 2.3.1 Inverting Buck-Boost Topology Concept
      2. 2.3.2 VIN and VOUT Range
      3. 2.3.3 Maximum Output Current
        1. 2.3.3.1 Thermal Limits
        2. 2.3.3.2 Stability Limits and Output Capacitor Selection
      4. 2.3.4 Design Precautions
      5. 2.3.5 Enable Pin Configuration
      6. 2.3.6 Power Good Pin Configuration
      7. 2.3.7 Discharging Output Voltage
      8. 2.3.8 Adjustable Soft-Start Time
      9. 2.3.9 Input Capacitor Selection
  8. 3Getting Started Hardware
  9. 4Testing and Results
  10. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 PCB Layout Recommendations
      1. 5.3.1 Layout Prints
    4. 5.4 Gerber Files
    5. 5.5 Assembly Drawings
  11. 6Related Documentation
  12. 7Trademarks
  13. 8Revision History

2.3.6 Power Good Pin Configuration

The TPS82130 has a built-in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG pin is an open-drain output that requires a pullup resistor. Because VOUT is the IC ground in this configuration, the PG pin is referenced to VOUT instead of ground, which means that the TPS82130 device pulls PG to VOUT when it is low.

This behavior can cause difficulties in reading the state of the PG pin, because in some applications the IC detecting the voltage level of the PG pin may not be able to withstand negative voltages. The level-shifter circuit shown in Figure 2-8 removes any difficulties associated with the offset PG pin voltages by eliminating the negative output signals of the PG pin. If the PG pin functionality is not required, it may be left floating or connected to VOUT without this circuit. Note that to avoid violating its absolute maximum rating, the PG pin should not be driven more than 6 V above the negative output voltage (IC ground).

GUID-397BB4AA-3E8A-47B2-9482-7FC2F4A62C63-low.svgFigure 2-8 PG Pin Level Shifter

Inside the TPS82130, the PG pin is connected to an N-channel MOSFET (Q3). By tying the PG pin to the gate of Q1, when the PG pin is pulled low, Q1 is off and Q2 is on because Q2's VGS is at VCC. SYS_PG is then pulled to ground.

When Q3 turns OFF, the gate of Q1 is pulled to ground potential which turns Q1 ON. This sequence of events pulls the gate of Q2 below ground, which turns it OFF. SYS_PG is then pulled up to the VCC voltage. Note that the VCC voltage must be at an appropriate logic level for the circuitry connected to the SYS_PG net.

Figure 4-19 and Figure 4-20 show this PG pin level-shifter sequence. The PG signal activates the PG pin level-shifter circuit and the G/D node signal represents the shared node between Q1 and Q2. This circuit has been tested with a VCC of 5 V and dual NFET Si1902DL. The SYS_PG net is the output of the circuit and goes between ground and 5 V and is easily read by a separate device.