JAJU459B December   2017  – November 2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Conditions of Use: Assumption
        1. 2.2.1.1 Generic Assumptions
        2. 2.2.1.2 Specific Assumptions
      2. 2.2.2 Diagnostics Coverage
        1. 2.2.2.1 Dual-Channel Monitoring
        2. 2.2.2.2 Checking ISO1211 Functionality With MCU (SIL1)
        3. 2.2.2.3 Checking TPS22919 Functionality With MCU (SIL1)
        4. 2.2.2.4 Checking TPS27S100 Functionality With MCU (SIL1)
        5. 2.2.2.5 Optional Monitoring Using RDY Pin of ISO5452, ISO5852S or UCC21750 Integrated Analog-to-PWM Isolated Sensor
      3. 2.2.3 Drive State
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO1211
      2. 2.3.2 TPS27S100
      3. 2.3.3 TPS22919
      4. 2.3.4 ISO5852S, ISO5452
    4. 2.4 System Design Theory
      1. 2.4.1 Digital Input Receiver for STO
      2. 2.4.2 STO_1 Signal Flow Path for Controlling VCC1
      3. 2.4.3 STO_2 Signal Flow Path
        1. 2.4.3.1 High-Side Switch for Controlling Secondary-Side Supply Voltage of Gate Driver
        2. 2.4.3.2 Powering up Secondary Side: VCC2 of Gate Driver
      4. 2.4.4 Gate Driver Design
      5. 2.4.5 STO_FB Signal Flow Path
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Getting Started Hardware
      1. 3.1.1 PCB Overview
    2. 3.2 Testing and Results
      1. 3.2.1 Logic High and Logic Low STO Thresholds
      2. 3.2.2 Validation of STO1 Signal
        1. 3.2.2.1 Propagation of STO1 to VCC1 of Gate Driver
        2. 3.2.2.2 1-ms STO Pulse Rejection
        3. 3.2.2.3 Diagnostic Pulses From MCU Interface
      3. 3.2.3 Validation of STO2 Signals
        1. 3.2.3.1 Propagation of STO2 to VCC2 of Gate Driver
        2. 3.2.3.2 1-ms Pulse Rejection
        3. 3.2.3.3 Diagnostic Pulses From MCU
        4. 3.2.3.4 Inrush Current Measurement
      4. 3.2.4 3.3-V Voltage Rail From Switcher
      5. 3.2.5 60-V Input Voltage and Reverse Polarity Protection
      6. 3.2.6 Validation of Trip Zone Functionality
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 Layer Plots
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
    1. 5.1 Trademarks
  11. 6About the Author
  12. 7Recognition
  13. 8Revision History

2.1 Block Diagram

Figure 2-1 shows the overall system. The system includes the TIDA-01599 reference design, a diagnostics MCU (SIL 1), which is not part of the TIDA-01599 design, an isolated DC|DC gate drive power supply TIDA-00199(1) and a three-phase IGBT power stage with CMOS input isolated gate drivers, as for example implemented with TIDA-00195(2).

Figure 2-1 System Block Diagram With TIDA-01599

The TIDA-01599 reference design incorporates dual 24-V isolated inputs through ISO1211 for the STO_1 and STO_2 signals. OSSD pulses are supported through low-pass filters which should reject STO pulses of less than 1 ms. The outputs of the STO_1 and STO_2 subsystem provide the corresponding supply voltage P24V and VCC. The STO_1 and STO_2 signals control the primary (VCC) and secondary (P24-V) side power supply to the six isolated IGBT gate drivers through a power switch TPS22919 and a high-side switch TPS27S100, respectively. P24V is the 24-V input voltage to the isolated DC|DC converter TIDA-00199. The TIDA-00199 board accepts 24 V with a tolerance of ±20% and provides four isolated sets (15 V, –8 V) of bias voltages. In this design, the TIDA-00199 is used to provide the bipolar supply to the secondary side of the six isolated IGBT gate drivers. VCC is the supply voltage to the primary logic side of the six isolated gate drivers.

As long as a logic 1 (+24-V DC) is present at both STO inputs, the motor is operable. If there is a logic 0 (0 V) at one or both of the STO inputs, the power supplies to the gate drivers are disconnected and the motor coasts down to zero. The use of 1oo2 architecture helps achieve HFT = 1 and only the occurrence of two simultaneous faults can cause failure of the safety function.

An STO_FB signal is provided to indicate the status of the drive (safe state or normal operation) and can be used to feedback the status of the drive to a safety PLC for additional diagnostics, if desired.

The diagnostic signals are routed to a 3.3-V LaunchPad™ compatible interface to connect an MCU (SIL 1) such as a C2000 MCU to run the corresponding diagnostic and monitoring software. The MCU (SIL 1) and the software are not part of this design.