JAJU510H March   2018  – December 2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5320
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC1305M05
      5. 2.2.5  OPA4340
      6. 2.2.6  LM76003
      7. 2.2.7  PTH08080W
      8. 2.2.8  TLV1117
      9. 2.2.9  OPA350
      10. 2.2.10 UCC14240
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
        6. 2.3.1.6 Thermal Considerations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Power Supplies
        1. 2.3.4.1 Main Input Power Conditioning
        2. 2.3.4.2 Isolated Bias Supplies
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading and Debugging the Firmware
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode - 230 VRMS, 400 V L-L
          1. 3.2.5.1.1 PFC Start-up – 230 VRMS, 400 L-L AC Voltage
          2. 3.2.5.1.2 Steady State Results at 230 VRMS, 400 V L-L - PFC Mode
          3. 3.2.5.1.3 Efficiency and THD Results at 220 VRMS, 50 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 PFC Mode - 120 VRMS, 208 V L-L
          1. 3.2.5.2.1 Steady State Results at 120 VRMS, 208 V-L-L - PFC Mode
          2. 3.2.5.2.2 Efficiency and THD Results at 120 VRMS - PFC Mode
        3. 3.2.5.3 Inverter Mode
          1. 3.2.5.3.1 Inverter Closed Loop Results
          2. 3.2.5.3.2 Efficiency and THD Results - Inverter Mode
          3. 3.2.5.3.3 Inverter - Transient Test
      6. 3.2.6 Open Loop Inverter Test Results
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Trademarks
  11. 6About the Authors
  12. 7Revision History

3.2.3.1 Lab 5

This is the first PFC lab. In this lab sensing is checked and no switching action occurs until clearPWMTrip is set to 1.

The hardware setup for the PFC mode is explained in Figure 3-17. TI recommends starting the PFC at low voltage like 30 VRMS and connecting a 2-kΩ resistor.

Set the project to Lab 5 by changing the Lab Number in the <settings.h> file, (this will be changed by powerSUITE GUI when using powerSUITE project).

Under this condition, the converter operates as a rectifier and rectified current can be observed being drawn without any power factor correction. SPLL locking can also be safely verified in this build.

Figure 3-18 Lab 5 Software Diagram

Hence, the following variables are put on the datalogger:

TINV_dVal1 = TINV_vGrid_A_sensed_pu;
TINV_dVal2 = TINV_angleSPLL_radians / (float32_t)(2.0f * TINV_PI);
TINV_dVal3 = TINV_vGrid_A_sensed_pu;
TINV_dVal4 = TINV_iInv_A_sensed_pu;
DLOG_4CH_run(&TINV_dLog1);

Make sure the Grid frequency is specified correctly, the grid frequency can be changed through the sysconfig page for powerSUITE based projects. If not powerSUITE based project one can modify the tinv_settings.h file. 

#define TINV_AC_FREQ_HZ ((float32_t)50)

Build and load the code, use the lab5.js file to populate the watch variables in the CCS window.

PLL lock can be checked by plotting the buffers, use the graph1.graphprop to see the buffer through Tools→ Graph → Dual Time.

Cosine transforms are used hence the angle will be 0 when the Vgrid as its peak.

First close the relay by writing a 1 to TINV_allRelaySet

Initially, the test may be run with only 30 VRMS for safety, hence safely ramp the AC supply to 30 VRMS and observe the graph in the CCS debug window to confirm the PLL is locking. Figure 3-19 shows low voltage phase locked loop check from watch window.

GUID-20210408-CA0I-8N4P-ZCTP-7SJGVQQB37Q7-low.png Figure 3-19 PLL - Grid Voltage Synchronization

If the PLL is not locking one may also issue a tinv_reset_PLL command by setting it to 1, this will initiate a task to zero out an integrated error in the module and zero all the memory elements.

Similarly, the current flowing from the grid across all phases can be checked, using the graph watch window of CCS. Figure 3-20 shows the Sensed grid currents from graph windowCheck for three phase grid currents observed from the watch window.

GUID-20210408-CA0I-XR79-DVKQ-BFJ2P5JLVFR4-low.png Figure 3-20 Sensed Grid Currents - PFC Mode

To verify boost action in Lab 5, follow the steps according to the sequence provided:

  • Turn on the auxiliary power supply and set it to 15 V and then debug and run the code.
  • Connect suitable load to the terminals J1 and J2. Make sure to use a high load resistance (around 2 kΩ) which otherwise can lead to high inrush currents triggering the overcurrent flag.
  • Apply 30 VRMS AC voltage to the three phase terminals
  • Immediately turn on the relay by writing a 1 to TINV_allRelaySet. Voltage should now start to appear across the DC terminals.
  • Clear the PWM trip by setting TINV_clearPwmTrip to 1 to see a slight boost in DC voltage.

Before PFC action begins, a rectified current will be drawn due to the load on the Vbus. As soon as clearPWMTrip is set to 1, a slight boost in DC voltage is seen. Note the input current has a double bump without the neutral connected to the source at light load.

Note:

There can be a situation in the labs for PFC (Lab 5, Lab 6, and Lab 7) where the converter operates as a rectifier and rectified current is seen being drawn without any power factor correction. But as soon as TINV_clearPwmTrip is set to 1, there is no switching action – the Gate Signals remain off.

This is because there is an overcurrent or DSAT flag (InvA_overcurrent, InvB_overcurrent,DSATA, DSATB) which is set in one of the three phases and this happens under three circumstances:

  1. On closing the relays, there is an inrush current which creates an overcurrent trip in one of the three phases.
  2. When TINV_clearPwmTrip to 1, the switching action causes one of the flags to be set.
  3. Setting TINV_StartpowerStage to 1 for closing the current and voltage loop.

The EPWM TZFLG is set to 0X000C and under this condition no switching occurs. So make sure the load resistance is increased so that the inrush currents will not cause a trip condition and the EPWM TZFLG changes from 0x0004 to 0x0000 and switching occurs.

Once the FLG is set to 0x000C, even if we do a TINV_reset_fault_status to reset the faults, though the faults may be cleared PWM action will not be observed.

The goal is, as soon as the auxiliary power supply is started and the code debugged, all the faults – namely InvA_overcurrent, InvB_overcurrent, DSATA, DSATB; and so forth – should be set to zero so that the controller does not go into a trip state.