JAJU510H March   2018  – December 2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5320
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC1305M05
      5. 2.2.5  OPA4340
      6. 2.2.6  LM76003
      7. 2.2.7  PTH08080W
      8. 2.2.8  TLV1117
      9. 2.2.9  OPA350
      10. 2.2.10 UCC14240
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
        6. 2.3.1.6 Thermal Considerations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Power Supplies
        1. 2.3.4.1 Main Input Power Conditioning
        2. 2.3.4.2 Isolated Bias Supplies
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading and Debugging the Firmware
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode - 230 VRMS, 400 V L-L
          1. 3.2.5.1.1 PFC Start-up – 230 VRMS, 400 L-L AC Voltage
          2. 3.2.5.1.2 Steady State Results at 230 VRMS, 400 V L-L - PFC Mode
          3. 3.2.5.1.3 Efficiency and THD Results at 220 VRMS, 50 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 PFC Mode - 120 VRMS, 208 V L-L
          1. 3.2.5.2.1 Steady State Results at 120 VRMS, 208 V-L-L - PFC Mode
          2. 3.2.5.2.2 Efficiency and THD Results at 120 VRMS - PFC Mode
        3. 3.2.5.3 Inverter Mode
          1. 3.2.5.3.1 Inverter Closed Loop Results
          2. 3.2.5.3.2 Efficiency and THD Results - Inverter Mode
          3. 3.2.5.3.3 Inverter - Transient Test
      6. 3.2.6 Open Loop Inverter Test Results
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Trademarks
  11. 6About the Authors
  12. 7Revision History

3.1.1.2 Microcontroller Resources Used on the Design

Table 3-1 details the key controller peripherals used for control of the power stage on the board and Table 3-2 lists the key connectors and functions.

Table 3-1 Key Controller Peripherals Used for Control of Power Stage on Board
Pin NumberDESCRIPTIONSOFTWARE NAME
15, 31, 28Grid Voltage Sense Phase A, B, CTINV_VGRID_A, B, C
21, 33, 30Inverter Side Voltage Phase A, B, CTINV_VINV_A, B, C
25, 37, 34Inverter Side Current Phase ATINV_IINV_A, B, C
42Bus Voltage SensingTINV_VBUS
40Bus Voltage Mid Point SensingTINV_VBUS_MID
12, 14, 18, 20Temperature A, B, C and AmbientTINV_TEMP_A, B, C, AMB
49, 50, 58Q1 PWM Phase A, B, CTINV_Q1_A, B, C
51, 52, 60Q3 PWM Phase A, B, CTINV_Q3_A, B, C
53, 54, 62Q2 PWM Phase A, B, CTINV_Q2_A, B, C
99, 103, 107SDFM Data IG A, B, CTINV_IGRID_A, B, C
101, 105, 109SDFM Clock IG A, B, C
57, 75SDFM Clock Source
89, 87 , 85SiC Fault Signal A, B, C (active Low)TINV_FAULT_A, B, C
86, 88, 90, 92Relay on A, B, C, NTINV_RELAY_A, B, C, N
61, 63Gate driver supply PWMTINV_GATE_DRIVE
59Control GPIO for FANTINV_FAN
108, 110These pins are used to see ISR nesting and so forth, on the docking station while starting firmware debug TINV_PROFILING1,2
95Gate driver enableTNV_PWM_EN
81Gate driver ResetTINV_R
Table 3-2 Key Connectors and Functions
CONNECTOR NAMEFUNCTION
J1, J2DC+ and DC– terminals
J3, J4, J31, J32Phases A, B, C and neutral terminals
J3315-V auxiliary power supply
J34Jumper for auxiliary power supply
J5, J13HSEC control card connector slot
J23, J7, J17, J14, J20Phase Agate driver card connector slot
J24, J15, J21, J9, J18Phase B gate driver card connector slot
J25, J16, J22, J12, J19Phase C gate driver card connector slot

The following lists shows the hardware changes to TIDA-01606 - REV-6.

  1. The resistors R1, R5, and R47 were changed to 2-mΩ current sense resistors.
  2. The current-sense resistors along with AMC1306M05 (U1, U5, and U8) is used for current sensing in this design. The current sense out phase A LEM sensor has a noise pick-up issue and therefore is not used for current sensing and running the control loop.
  3. Replaced R146, R149, R152 to 33 Ω.
  4. On the TIDA-01606E4-ISOHVCARD, replaced R18 to 15-k Ω and R26 to 0 Ω.