JAJU510H March   2018  – December 2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5320
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC1305M05
      5. 2.2.5  OPA4340
      6. 2.2.6  LM76003
      7. 2.2.7  PTH08080W
      8. 2.2.8  TLV1117
      9. 2.2.9  OPA350
      10. 2.2.10 UCC14240
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
        6. 2.3.1.6 Thermal Considerations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Power Supplies
        1. 2.3.4.1 Main Input Power Conditioning
        2. 2.3.4.2 Isolated Bias Supplies
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading and Debugging the Firmware
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode - 230 VRMS, 400 V L-L
          1. 3.2.5.1.1 PFC Start-up – 230 VRMS, 400 L-L AC Voltage
          2. 3.2.5.1.2 Steady State Results at 230 VRMS, 400 V L-L - PFC Mode
          3. 3.2.5.1.3 Efficiency and THD Results at 220 VRMS, 50 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 PFC Mode - 120 VRMS, 208 V L-L
          1. 3.2.5.2.1 Steady State Results at 120 VRMS, 208 V-L-L - PFC Mode
          2. 3.2.5.2.2 Efficiency and THD Results at 120 VRMS - PFC Mode
        3. 3.2.5.3 Inverter Mode
          1. 3.2.5.3.1 Inverter Closed Loop Results
          2. 3.2.5.3.2 Efficiency and THD Results - Inverter Mode
          3. 3.2.5.3.3 Inverter - Transient Test
      6. 3.2.6 Open Loop Inverter Test Results
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Trademarks
  11. 6About the Authors
  12. 7Revision History

2.2.3 TMS320F28379D

The Delfino™ TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications. Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000™ portfolio, the F2837xD supports a new dual-core C28x architecture that significantly boosts system performance. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems.

  • Dual-core architecture:
    • Two TMS320C28x 32-bit CPUs
    • 200 MHz
    • IEEE 754 single-precision floating-point unit (FPU)
    • Trigonometric math unit (TMU)
    • Viterbi/complex math unit (VCU-II)
  • Two programmable control law accelerators (CLAs)
    • 200 MHz
    • IEEE 754 single-precision floating-point instructions
    • Executes code independently of main CPU
  • On-chip memory
    • 512KB (256 kW) or 1MB (512 kW) of Flash (ECC-protected)
    • 172KB (86 kW) or 204KB (102 kW) of RAM (ECC-protected or parity-protected)
    • Dual-zone security supporting third-party development
  • Clock and system control:
    • Two internal zero-pin 10-MHz oscillators
    • On-chip crystal oscillator
    • Windowed watchdog timer module
    • Missing clock detection circuitry
  • 1.2-V core, 3.3-V I/O design
  • System peripherals:
    • Two external memory interfaces (EMIFs) with ASRAM and SDRAM support
    • Dual six-channel direct memory access (DMA) controllers
    • Up to 169 individually programmable, multiplexed general-purpose input/output (GPIO) pins with input filtering
    • Expanded peripheral interrupt controller (ePIE)
    • Multiple low-power mode (LPM) support with external wakeup
  • Communications peripherals:
    • USB 2.0 (MAC + PHY)
    • Support for 12-pin 3.3-V compatible universal parallel port (uPP) interface
    • Two controller area network (CAN) modules (pin-bootable)
    • Three high-speed (up to 50-MHz) SPI ports (pin-bootable)
    • Two multichannel buffered serial ports (McBSPs)
    • Four serial communications interfaces (SCI/UART) (pin-bootable)
    • Two I2C interfaces (pin-bootable)
  • Analog subsystem:
    • Up to four analog-to-digital converters (ADCs):
      • 16-bit mode
        • 1.1 MSPS each (up to 4.4-MSPS system throughput)
        • Differential inputs
        • Up to 12 external channels
      • 12-bit mode
        • 3.5 MSPS each (up to 14-MSPS system throughput)
        • Single-ended inputs
        • Up to 24 external channels
      • Single sample-and-hold (S/H) on each ADC
      • Hardware-integrated post-processing of ADC conversions:
        • Saturating offset calibration
        • Error from setpoint calculation
        • High, low, and zero-crossing compare, with interrupt capability
        • Trigger-to-sample delay capture
    • Eight windowed comparators with 12-bit digital-to-analog converter (DAC) references
    • Three 12-bit buffered DAC outputs
  • Enhanced control peripherals:
    • 24 pulse width modulator (PWM) channels with enhanced features
    • 16 high-resolution pulse width modulator (HRPWM) channels:
      • High resolution on both A and B channels of eight PWM modules
      • Dead-band support (on both standard and high resolution)
    • Six enhanced capture (eCAP) modules
    • Three enhanced quadrature encoder pulse (eQEP) modules
    • Eight sigma-delta filter module (SDFM) input channels, two parallel filters per channel:
      • Standard SDFM data filtering
      • Comparator filter for fast action for out of range
GUID-40208217-C550-4462-8C3B-DB7FAA5C68DB-low.gifFigure 2-4 TMS320F28379D Functional Block Diagram