JAJU528B August   2022  – January 2023 OPA388-Q1

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagrams
    2. 2.2 Highlighted Products
      1. 2.2.1 TPSI2140-Q1
      2. 2.2.2 AMC1301-Q1
      3. 2.2.3 SN6501-Q1
    3. 2.3 System Design Theory
      1. 2.3.1 Isolation Leakage Current Theory
      2. 2.3.2 High-Voltage Measurement
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Required Hardware
    2.     Hardware with Solid-State Relay
    3. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Isolation Tests
        1. 3.2.2.1 Normal Conditions
        2. 3.2.2.2 Isolation Error at HV Positive
        3. 3.2.2.3 Isolation Error at HV Negative
        4. 3.2.2.4 Isolation Error at ¼ HV Battery Voltage
        5. 3.2.2.5 Isolation Error at ¾ HV Battery Voltage
        6. 3.2.2.6 Isolation Error at the Middle of an HV Battery Voltage
      3. 3.2.3 Solid-State Relay Isolation Tests
        1. 3.2.3.1 Normal Conditions
        2. 3.2.3.2 Isolation Error at HV Positive
        3. 3.2.3.3 Isolation Error at HV Negative
        4. 3.2.3.4 Isolation Error at ¼ HV Battery Voltage
        5. 3.2.3.5 Isolation Error at ¾ HV Battery Voltage
        6. 3.2.3.6 Isolation Error at the Middle of an HV Battery Voltage
      4. 3.2.4 High Voltage Measurements
      5. 3.2.5 Isolation Measurement Analysis
      6. 3.2.6 Error Analysis
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
  12. 7Trademarks
  13. 8Revision History

3.2.2.3 Isolation Error at HV Negative

An error condition is created by connecting the HV negative line to chassis ground. To understand the behavior of error conditions, measurements were performed at different battery voltages.

GUID-7A33C926-A69F-47FA-9F4B-99FCF1940B32-low.gifFigure 3-15 HV Negative Error 400 V at No Resistance
No resistance from HV negative line to chassis ground
CH1: ISO_POS
CH2: ISO_NEG
CH3: RELAY_NEG
CH4: RELAY_POS
GUID-EE29A05C-7D31-4566-9370-6D8098151A1C-low.gifFigure 3-16 HV Negative Error 400 V at 100-kΩ Resistance
100-kΩ resistance from positive line to chassis ground
CH1: ISO_POS
CH2: ISO_NEG
CH3: RELAY_NEG
CH4: RELAY_POS
Table 3-3 Measurements at HV Negative Error
HV BATTERY VOLTAGE
(SUPPLIED AND MEASURED)		MEASURED REFERENCE VOLTAGEMEASURED PEAK ISO_POS VOLTAGEMEASURED PEAK ISO_NEG VOLTAGE
100.0062.5052.1912.61
150.0082.5041.9822.61
200.0032.5041.7742.61
250.0042.5041.5652.61
300.0042.5041.3572.61
350.0042.5041.1482.61
400.0062.5040.9392.61
450.0072.5040.7312.61

Figure 3-17 shows the deviations of HV POS and HV NEG ADC voltages from the normal conditions. HV NEG ADC is slightly above the reference voltage and constant when U7 (negative relay) is closed. This behavior is observable only when the HV negative line is low ohmic or short to chassis ground.

GUID-2ED41467-814C-4F09-A834-6C6CE79FD8A6-low.gifFigure 3-17 Behavior for HV Negative Isolation Error