JAJU528B August   2022  – January 2023 OPA388-Q1

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagrams
    2. 2.2 Highlighted Products
      1. 2.2.1 TPSI2140-Q1
      2. 2.2.2 AMC1301-Q1
      3. 2.2.3 SN6501-Q1
    3. 2.3 System Design Theory
      1. 2.3.1 Isolation Leakage Current Theory
      2. 2.3.2 High-Voltage Measurement
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Required Hardware
    2.     Hardware with Solid-State Relay
    3. 3.2 Testing and Results
      1. 3.2.1 Test Setup
      2. 3.2.2 Isolation Tests
        1. 3.2.2.1 Normal Conditions
        2. 3.2.2.2 Isolation Error at HV Positive
        3. 3.2.2.3 Isolation Error at HV Negative
        4. 3.2.2.4 Isolation Error at ¼ HV Battery Voltage
        5. 3.2.2.5 Isolation Error at ¾ HV Battery Voltage
        6. 3.2.2.6 Isolation Error at the Middle of an HV Battery Voltage
      3. 3.2.3 Solid-State Relay Isolation Tests
        1. 3.2.3.1 Normal Conditions
        2. 3.2.3.2 Isolation Error at HV Positive
        3. 3.2.3.3 Isolation Error at HV Negative
        4. 3.2.3.4 Isolation Error at ¼ HV Battery Voltage
        5. 3.2.3.5 Isolation Error at ¾ HV Battery Voltage
        6. 3.2.3.6 Isolation Error at the Middle of an HV Battery Voltage
      4. 3.2.4 High Voltage Measurements
      5. 3.2.5 Isolation Measurement Analysis
      6. 3.2.6 Error Analysis
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
  12. 7Trademarks
  13. 8Revision History

2.2.1 TPSI2140-Q1

The TPSI2140-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. The primary side of the device consists of four differential drivers which deliver power and enable logic information to each of the internal MOSFETs on the secondary side. This device uses capacitive isolation technology in combination with its internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply. When the enable pin is brought HI, the oscillator starts and the drivers send power and a logic HI across the barrier. When the enable pin is brought LO or the VDD falls below the UVLO threshold, the drivers are disabled. The lack of activity communicates a logic LO to the secondary side and the MOSFETs are disabled.

Figure 2-3 TPSI2140-Q1 Block Diagram

Key features include:

  • Integrated MOSFETs with 2-mA avalanche rating
  • 1200-V standoff voltage
  • RON = 130 Ω (TJ = 25°C)
  • TON, TOFF < 700 μs
  • Isolation rating, VISO, up to 3750 VRMS / 5300 VDC
  • Low primary side supply current, 9-mA ON state current, 3.5-μA OFF state current