JAJU680A January   2019  – July 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Flow Measurement
      2. 2.2.2 ToF Measurement
        1. 2.2.2.1 ADC-Based Acquisition Process
        2. 2.2.2.2 Ultrasonic Sensing Flow-Metering Library
      3. 2.2.3 Low-Power Design
        1. 2.2.3.1 Energy-Efficient Software
        2. 2.2.3.2 Optimized Hardware Design
        3. 2.2.3.3 Efficient Use of FRAM
        4. 2.2.3.4 The LEA Advantage
    3. 2.3 Highlighted Products
      1. 2.3.1 MSP430FR6043
      2. 2.3.2 OPA836 and OPA838
      3. 2.3.3 TS5A9411
    4. 2.4 System Design Theory
      1. 2.4.1 Signal Processing for ToF
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 EVM430-FR6043
      2. 3.1.2 Software
        1. 3.1.2.1 MSP Driver Library (MSP DriverLib)
        2. 3.1.2.2 Ultrasonic Sensing Flow Metering Library
        3. 3.1.2.3 Application
          1. 3.1.2.3.1 Application Customization
          2. 3.1.2.3.2 LCD Stand-Alone Mode
        4. 3.1.2.4 USS Design Center (PC GUI)
      3. 3.1.3 Transducer and Meter
        1. 3.1.3.1 Frequency Characterization of Transducer and Meter
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
        1. 3.2.1.1 Connecting Hardware
        2. 3.2.1.2 Building and Loading Software
          1. 3.2.1.2.1 Using Code Composer Studio IDE
          2. 3.2.1.2.2 Using IAR Embedded Workbench IDE
        3. 3.2.1.3 Executing Application
        4. 3.2.1.4 Configure Device and Observe Results Using GUI
        5. 3.2.1.5 Customization and Optimization
      2. 3.2.2 Test Results
        1. 3.2.2.1 Single-Shot Standard Deviation
        2. 3.2.2.2 Zero-Flow Drift
        3. 3.2.2.3 Absolute Time of Flight Measurements
        4. 3.2.2.4 Variability in Zero Flow Drift Across Transducers
        5. 3.2.2.5 Flow Measurements
        6. 3.2.2.6 Average Current Consumption
        7. 3.2.2.7 Memory Footprint
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 Bill of Materials
      3. 4.1.3 PCB Layout Recommendations
        1. 4.1.3.1 Layout Prints
      4. 4.1.4 Altium Project
      5. 4.1.5 Gerber Files
      6. 4.1.6 Assembly Drawings
    2. 4.2 Software Files
    3. 4.3 Related Documentation
    4. 4.4 Terminology
    5. 4.5 Trademarks
    6. 4.6 サポート・リソース
  10. 5About the Authors
  11. 6Revision History

2.3.2 OPA836 and OPA838

The OPA836 is a single, ultra-low power, rail-to-rail output, negative-rail input, voltage-feedback (VFB) operational amplifiers that operate over a power-supply range of 2.5 V to 5.5 V with a single supply or with ±1.25 V to ±2.75 V with a dual supply. Consuming only 1 mA per channel and with a unity-gain bandwidth of 205 MHz, this amplifier sets an industry-leading power-to-performance ratio for rail-to-rail amplifiers. Coupled with a power-savings mode to reduce current to <1.5 µA, this device offers an attractive solution for high-frequency amplifiers in power-sensitive applications.

The TIDM-02003 design uses an OPA836 to implement an efficient two-stage amplifier providing the desired gain and bandwidth. A high-gain first stage amplifier is implemented using an OPA836 for the following reasons:

  • Low input noise (4.6 nV/√ Hz at 100 kHz)
  • High bandwidth (205 MHz)
  • Low power consumption: 0.5 µA in power-down mode and 1-mA quiescent current

Because the gain of the second stage amplifier is lower than the first stage, the low input noise and bandwidth requirements are not as critical. The MSP430FR6043 internal programmable gain amplifier (PGA) is used to provide the second stage amplification from –6.5 dB to 30.8 dB.

The OPA838 can provide enhanced standard deviation performance up to 2.5x lower than the OPA836 and is a drop-in replacement.