JAJU802A January   2022  – October 2022

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TMS320F2800137
      2. 2.3.2 TMS320F280025C
      3. 2.3.3 TMS320F280039C
      4. 2.3.4 UCC28740
      5. 2.3.5 UCC27517
      6. 2.3.6 TLV9062
      7. 2.3.7 TLV76733
    4. 2.4 System Design Theory
      1. 2.4.1 Interleaved PFC
        1. 2.4.1.1 Full Bridge Diode Rectifier Rating
        2. 2.4.1.2 Inductor Ratings
        3. 2.4.1.3 AC Voltage Sensing
        4. 2.4.1.4 DC Link Voltage Sensing
        5. 2.4.1.5 Bus Current Sensing
        6. 2.4.1.6 DC Link Capacitor Rating
        7. 2.4.1.7 MOSFET Ratings
        8. 2.4.1.8 Diode Ratings
      2. 2.4.2 Three-Phase PMSM Drive
        1. 2.4.2.1 Field Oriented Control of PM Synchronous Motor
        2. 2.4.2.2 Sensorless Control of PM Synchronous Motor
          1. 2.4.2.2.1 Enhanced Sliding Mode Observer with Phase Locked Loop
            1. 2.4.2.2.1.1 Mathematical Model and FOC Structure of an IPMSM
            2. 2.4.2.2.1.2 Design of ESMO for the IPMSM
            3. 2.4.2.2.1.3 Rotor Position and Speed Estimation with PLL
        3. 2.4.2.3 Field Weakening (FW) and Maximum Torque Per Ampere (MTPA) Control
        4. 2.4.2.4 Compressor Drive with Automatic Vibration Compensation
        5. 2.4.2.5 Fan Drive with Flying Start
        6. 2.4.2.6 Hardware Prerequisites for Motor Drive
          1. 2.4.2.6.1 Motor Current Feedback
            1. 2.4.2.6.1.1 Current Sensing with Three-Shunt
            2. 2.4.2.6.1.2 Current Sensing with Single-Shunt
          2. 2.4.2.6.2 Motor Voltage Feedback
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Getting Started Hardware
      1. 3.1.1 Hardware Board Overview
      2. 3.1.2 Test Conditions
      3. 3.1.3 Test Equipment Required for Board Validation
      4. 3.1.4 Test Setup
    2. 3.2 Getting Started Firmware
      1. 3.2.1 Download and Install Software Required for Board Test
      2. 3.2.2 Opening Project Inside CCS
      3. 3.2.3 Project Structure
    3. 3.3 Test Procedure
      1. 3.3.1 Build Level 1: CPU and Board Setup
        1. 3.3.1.1 Start CCS and Open Project
        2. 3.3.1.2 Build and Load Project
        3. 3.3.1.3 Setup Debug Environment Windows
        4. 3.3.1.4 Run the Code
      2. 3.3.2 Build Level 2: Open Loop Check with ADC Feedback
        1. 3.3.2.1 Start CCS and Open Project
        2. 3.3.2.2 Build and Load Project
        3. 3.3.2.3 Setup Debug Environment Windows
        4. 3.3.2.4 Run the Code
      3. 3.3.3 Build Level 3: Closed Current Loop Check
        1. 3.3.3.1 Start CCS and Open Project
        2. 3.3.3.2 Build and Load Project
        3. 3.3.3.3 Setup Debug Environment Windows
        4. 3.3.3.4 Run the Code
      4. 3.3.4 Build Level 4: Full PFC and Motor Drive Control
        1. 3.3.4.1  Start CCS and Open Project
        2. 3.3.4.2  Build and Load Project
        3. 3.3.4.3  Setup Debug Environment Windows
        4. 3.3.4.4  Run the Code
        5. 3.3.4.5  Run the System
        6. 3.3.4.6  Tuning Motor Drive FOC Parameters
        7. 3.3.4.7  Tuning PFC Parameters
        8. 3.3.4.8  Tuning Field Weakening and MTPA Control Parameters
        9. 3.3.4.9  Tuning Flying Start Control Parameters
        10. 3.3.4.10 Tuning Vibration Compensation Parameters
        11. 3.3.4.11 Tuning Current Sensing Parameters
    4. 3.4 Test Results
      1. 3.4.1 Performance Data and Curves
      2. 3.4.2 Functional Waveforms
      3. 3.4.3 Transient Waveforms
      4. 3.4.4 MCU CPU Load, Memory and Peripherals Usage
        1. 3.4.4.1 CPU Load for Full Implementation
        2. 3.4.4.2 Memory Usage
        3. 3.4.4.3 Peripherals Usage
    5. 3.5 Migrate Firmware to a New Hardware Board
      1. 3.5.1 Configure the PWM, CMPSS, and ADC Modules
      2. 3.5.2 Setup Hardware Board Parameters
      3. 3.5.3 Configure Faults Protection Parameters
      4. 3.5.4 Setup Motor Electrical Parameters
      5. 3.5.5 Setup PFC Control Parameters
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 Bill of Materials
      3. 4.1.3 Altium Project
      4. 4.1.4 Gerber Files
      5. 4.1.5 PCB Layout Guidelines
    2. 4.2 Software Files
    3. 4.3 Documentation Support
    4. 4.4 サポート・リソース
    5. 4.5 Trademarks
  10. 5Terminology
  11. 6Revision History

2.4.1 Interleaved PFC

Boost converter is the most popular topology for PFC application. This is because boost converters have continuous input current that can be controlled with average current mode control to force input current to track changes in line voltage. Also higher inherent efficiency and wide duty cycle range makes it more attractive than buck-boost converter.

While basic single phase boost converter is adequate for low power non-isolated application, interleaving techniques provide additional advantages in high power motor drive application. The two phase interleaved boost converter is simply two boost converters in parallel operating 180° out of phase. The input current is the sum of the two inductor currents IL1 and IL2. Because the inductor’s ripple currents are out of phase, they tend to cancel each other and reduce the input ripple current caused by the boost inductors. The best input inductor ripple current cancellation occurs at 50 percent duty cycle. The output capacitor current is the sum of the two diode currents (ID1 + ID2) less the dc output current. Interleaving reduces the output capacitor ripple current ( IOUT) as a function of duty cycle. As the duty cycle approaches 0 percent, 50 percent and 100 percent duty cycle, the sum of the two diode currents approaches dc. At these points, the output capacitor only has to filter the inductor ripple current.