JAJU812 March   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multichannel SSR with Independent Isolation Between SSR Channels
      2. 2.2.2 Design Challenge With Single Isolation
      3. 2.2.3 Multichannel SSR Drive With Single Isolation Multichannel Digital Isolator
      4. 2.2.4 Need of High-Impedance Voltage Translator
      5. 2.2.5 Design to Minimize Cross-Coupling and MOSFET Gate Pick up Due to Other SSR Switching
      6. 2.2.6 Schematic: Design of Gate-Drive Circuit
        1. 2.2.6.1 Calculation of Gate-Driver Power Consumption
      7. 2.2.7 Schematic: Digital Isolator Circuit
      8. 2.2.8 Schematic: 3.3 V to 10V_ISO, 5V_ISO Power Supply
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO7760
      2. 2.3.2 ISO7740
      3. 2.3.3 ISO7041
      4. 2.3.4 CSD19538Q2
      5. 2.3.5 CSD17382F4
      6. 2.3.6 TPL7407LA
      7. 2.3.7 TLV760
      8. 2.3.8 TLC555
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Test Equipment Needed to Validate Board
      2. 3.1.2 Test Conditions
      3. 3.1.3 Test Procedure
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Functional Tests
      2. 3.3.2 Overcurrent Testing With External Fuse
      3. 3.3.3 Surge Testing
      4. 3.3.4 Multichannel SSR Driven From Two 24-VAC Transformers
      5. 3.3.5 Alternate SSR Topology for High Voltage
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

2.2.4 Need of High-Impedance Voltage Translator

The reference design SSR topology uses the high impedance voltage translator connected between the digital isolator and the SSR MOSFET gate. Figure 2-7 illustrates the high-impedance voltage translator consists of a PNP transistor (QP) and an NPN transistor (QN).

GUID-20210210-CA0I-VPL5-RCL6-1SXMXG9KPQVZ-low.gif Figure 2-7 High Impedance Voltage Translator for Driving Multiple SSR With Single Isolating Element
When SSR is switching, the voltage across the blocking diode (D) changes. For a 24-VAC supply, the peak voltage across the blocking diode could be as high as 41 V (considering 20% tolerance on the AC voltage supply). The same voltage level appears across the PNP transistor (QP), and hence the PNP transistor has to be rated more than 41 V with sufficient voltage margin. If the digital isolator is used directly to turn on the SSR, the higher voltage will damage the output structure of isolator.

The NPN and the PNP transistor circuit forms the voltage translator circuit, translating the 5 V at the digital isolator output to a higher voltage for the MOSFET gate drive. It is also required that the off-state leakage of the PNP transistor has to be very low so that the resulting voltage drop across the resistor between the gate and source of the SSR MOSFET, is sufficiently less than the worst-case gate threshold voltage of MOSFETs.