JAJU812 March   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multichannel SSR with Independent Isolation Between SSR Channels
      2. 2.2.2 Design Challenge With Single Isolation
      3. 2.2.3 Multichannel SSR Drive With Single Isolation Multichannel Digital Isolator
      4. 2.2.4 Need of High-Impedance Voltage Translator
      5. 2.2.5 Design to Minimize Cross-Coupling and MOSFET Gate Pick up Due to Other SSR Switching
      6. 2.2.6 Schematic: Design of Gate-Drive Circuit
        1. 2.2.6.1 Calculation of Gate-Driver Power Consumption
      7. 2.2.7 Schematic: Digital Isolator Circuit
      8. 2.2.8 Schematic: 3.3 V to 10V_ISO, 5V_ISO Power Supply
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO7760
      2. 2.3.2 ISO7740
      3. 2.3.3 ISO7041
      4. 2.3.4 CSD19538Q2
      5. 2.3.5 CSD17382F4
      6. 2.3.6 TPL7407LA
      7. 2.3.7 TLV760
      8. 2.3.8 TLC555
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Test Equipment Needed to Validate Board
      2. 3.1.2 Test Conditions
      3. 3.1.3 Test Procedure
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Functional Tests
      2. 3.3.2 Overcurrent Testing With External Fuse
      3. 3.3.3 Surge Testing
      4. 3.3.4 Multichannel SSR Driven From Two 24-VAC Transformers
      5. 3.3.5 Alternate SSR Topology for High Voltage
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 サポート・リソース
    4. 4.4 Trademarks
  10. 5About the Author

2.2.6.1 Calculation of Gate-Driver Power Consumption

The gate-driver current consumption is calculated based on the following assumptions:

  • Digital isolator primary side voltage = 3.3 V
  • Digital Isolator secondary side voltage = 5 V
  • Gate drive PNP transistor power supply voltage = 8.5 V
  • The SSR MOSFET gate current consumption during switching is neglected.
  • The AC current of digital isolators are neglected, as the SSRs are expected to be switching at a very low rate and the digital isolator AC current is negligible.
  • The on-state voltage drop across PNP transistor Q2 is neglected

ISO7760 secondary current (Vi = Vcc), ICC2_ISO7760 = 3.3 mA.

ISO7740 secondary current (Vi = Vcc), ICC2_ISO7740 = 2.2 mA.

Gate current of single SSR, with 10-kΩ resistor across MOSFET gate and source, IG = (8.5 – 0.7) V / 10 kΩ = 780 µA.

PNP transistor biasing current, IBIAS = 8.5 V / (10 kΩ + 100 kΩ) = 77.3 µA.

Secondary side total gate drive current (approximate) with all SSR on, IGD_ON = 3.3 mA + 2.2 mA + (10 × (780 + 77.3) µA) = 14.07 mA.

Secondary side total gate drive current (approximate) with all SSR off, IGD_OFF = 3.3 mA + 2.2 mA = 5.5 mA.

The current consumption can be reduced by increasing the resistance across the gate-to-source terminals of the MOSFET, at the expense of increased SSR turn off time.