JAJU819B April   2021  – June 2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  7. 2System Description
    1. 2.1 Key System Specifications
  8. 3System Overview
    1. 3.1 Block Diagram
    2. 3.2 Design Considerations
      1. 3.2.1 Basic Operation
      2. 3.2.2 PCMC PSFB using C2000
    3. 3.3 System Design Theory
      1. 3.3.1 Peak Current Mode Control (PCMC) Implementation
      2. 3.3.2 Zero Voltage Switching (ZVS) or Low Voltage Switching (LVS)
      3. 3.3.3 Synchronous Rectification
      4. 3.3.4 Slope Compensation
    4. 3.4 Highlighted Products
      1. 3.4.1 C2000™ MCU F28004x
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Required Hardware and Software
      1. 4.1.1 Hardware
      2. 4.1.2 Software
        1. 4.1.2.1 Software Control Flow
        2. 4.1.2.2 Incremental Builds
        3. 4.1.2.3 Procedure for running the incremental builds - PCMC
          1. 4.1.2.3.1 Build 1: Peak Current Loop Check with Open Voltage Loop
            1. 4.1.2.3.1.1 Objective
            2. 4.1.2.3.1.2 Overview
            3. 4.1.2.3.1.3 Procedure
              1. 4.1.2.3.1.3.1 Start CCS and Open a Project
              2. 4.1.2.3.1.3.2 Build and Load the Project
              3. 4.1.2.3.1.3.3 Debug Environment Windows
              4. 4.1.2.3.1.3.4 Using Real-Time Emulation
              5. 4.1.2.3.1.3.5 Run the Code
          2. 4.1.2.3.2 Build 2: Closed current and voltage loop (Full PSFB)
            1. 4.1.2.3.2.1 Objective
            2. 4.1.2.3.2.2 Overview
            3. 4.1.2.3.2.3 Procedure
              1. 4.1.2.3.2.3.1 Build and Load Project
              2. 4.1.2.3.2.3.2 Debug Environment Windows
              3. 4.1.2.3.2.3.3 Run the Code
      3. 4.1.3 Test results
  10. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Software
    3. 5.3 Documentation Support
  11. 6Terminology
  12. 7About the Author
  13. 8Revision History

4.1.1 Hardware

Figure 4-1 shows key hardware components. This hardware uses the kit of Bidirectional 400-V/12-V DC/DC Converter Reference Design as the base board and with some modification for peak current mode control.

GUID-5D237903-1D04-47D0-BFF3-01AA5E4190D1-low.gif Figure 4-1 TIDM-02000 hardware

The key signal connections between the controlCARD and the base board are listed in the Table 4-1

Table 4-1 Key Signal Connections

SIGNAL NAME

DESCRIPTOIN

CONNECTION TO CONTROLCARD
ePWM-1A PWM drive for full-bridge switch Q2 GPIO-00
ePWM-1B PWM drive for full-bridge switch Q3 GPIO-01
ePWM-2A PWM drive for full-bridge switch Q1 GPIO-02
ePWM-2B PWM drive for full-bridge switch Q4 GPIO-03
ePWM-4A PWM drive for sync rectifier/push-pull switch Q6 GPIO-07
ePWM-4B PWM drive for sync-rectifier/push-pull switch Q5 GPIO-06
VLV-FB Low voltage bus – voltage feedback ADC-A0
ILV-FB Low voltage current feedback (Jumper J2 populated) ADC-B3/COMP2A
ILV-FILT Heavily filtered low voltage current feedback ADC-B2
VHV-FB High voltage bus – voltage feedback ADC-B1
IHV-FB Transformer high voltage winding current ADC-A2/COMP1A
IHV-FILT Heavily filtered transformer high voltage winding current ADC-A1

This board provides a lot of jumper options for experimentation but there are some jumpers that must be populated for proper operation of the board. These jumpers that must be populated are listed below:

C:JPG1, E:JPG1, J2, J5, J6, J7, J8, J10, J11, J12, J13, J15, J16, and J19.

Some hardware modifications are required by the customer before running the reference code in this board.

GUID-20201007-CA0I-TWCS-PCBX-SPPQCB3ZF058-low.gifFigure 4-2 Peak Current Sensing Circuit
  1. Remove resistor R50 in Figure 4-2. The heavily filtered winding current of the CT on the secondary side is used for average current mode control. For peak current mode control, a relatively low cutoff frequency filter is needed. Existence of R50 can introduce distortion to the current waveform.

Notes: Some magnetic components in the original board are replaced for peak current mode control as shown in Table 4-2.

Table 4-2 Current and Original magnetic Components

CURRENT

ORIGINAL

Main transformerMPS P6524_AVITEC AF5551R
Secondary side inductorVITEC 6193RVITEC AF5666BR
Shim inductorVITEC 6194RVITEC AF5667BR

ControlCARD settings:

Certain settings on the device control card are required to communicate over JTAG and use the isolated UART port. The user must also provide a correct ADC reference voltage. The following settings are required for revision A of the TMS320F280049C control card (refer to the info sheet located at \c2000ware\boards\controlCARDs\TMDSCNCD280049C.

  1. Set both ends of S1:A on the control card to ON (up) position to enable JTAG connection to the device and UART connection for SFRA GUI. If this switch is OFF (down), the user cannot use the isolated JTAG built in on the control card, nor can the SFRA GUI communicate with the device.
  2. Connect the USB cable to J1:A to communicate with the device from a host PC on which CCS runs.
  3. For the control loop, use the internal reference of the TMS320F28004x and move the S8 switch to the left (that is, pointing to VREFHI).
  4. For best performance of this reference design, remove the capacitor connected between the isolated grounds on the control card, C26:A.