JAJU821 December   2021

 

  1.   概要
  2.   リソース
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Overview
    1. 1.1 Key System Level Specifications
    2. 1.2 System Description
    3. 1.3 Block Diagram
    4. 1.4 Design Considerations
      1. 1.4.1 Frequency Band and Applications
        1. 1.4.1.1 RF Transceiver Synchronization Challenges
        2. 1.4.1.2 JESD204B-Compliant Multichannel Phase Synchronized Clocks Generation
      2. 1.4.2 Clock Jitter and System SNR
      3. 1.4.3 Power-Supply Selection
      4. 1.4.4 Highlighted Products
        1. 1.4.4.1 AFE7950
        2. 1.4.4.2 LMX2820
        3. 1.4.4.3 LMK04832
        4. 1.4.4.4 TPS62913 and TPS62912
        5. 1.4.4.5 LMK1C1104
  7. 2Hardware, Software, Testing Requirements, and Test Results
    1. 2.1 Required Hardware and Software
      1. 2.1.1 Hardware
        1. 2.1.1.1 Clocking Board Setup
        2. 2.1.1.2 FMC-to-FMC Adapter Board Setup
        3. 2.1.1.3 AFE7950EVM Setup
        4. 2.1.1.4 TSW14J56EVM Setup
        5. 2.1.1.5 Hardware Setup of Multiple Transceiver Synchronization
      2. 2.1.2 Software
        1. 2.1.2.1 TIDA-010230 Clocking Board GUI
        2. 2.1.2.2 AFE7950 EVM GUI
        3. 2.1.2.3 High-Speed Data Converter (HSDC) Pro
        4. 2.1.2.4 Programming Steps
        5. 2.1.2.5 Clocking Board Programming Sequence
        6. 2.1.2.6 Latte SW and HSDC Pro Setup
    2. 2.2 Test Setup
    3. 2.3 Test Results
      1. 2.3.1 LMX2820 Phase-Noise Performance
      2. 2.3.2 AFE7950 Transmitter Performance
      3. 2.3.3 AFE7950 Receiver Performance
      4. 2.3.4 Multiple AFE7950s TX and RX Alignment
      5. 2.3.5 Summary and Conclusion
  8. 3Design and Documentation Support
    1. 3.1 Design Files
      1. 3.1.1 Schematics
      2. 3.1.2 BOM
    2. 3.2 Tools and Software
    3. 3.3 Documentation Support
    4. 3.4 サポート・リソース
    5. 3.5 Trademarks
  9. 4About the Author
  10. 5Acknowledgement

1.4.3 Power-Supply Selection

In this design, RF PLL LMX2820 is used as a frequency synthesizer for clocking the data converter. The LMX2820 requires lower clock jitter and therefore lower phase noise to generate the required higher sampling clocks. Phase noise is directly impacted by the power supply noise and ripple.

This design has included both the 3.3-V supply options from high efficiency, low noise and low-ripple synchronous buck converter (TPS62913) and high-accuracy low noise LDO (TPS7A5301). The LMX2820 phase-noise performance measured with both supply options and results shows very equivalent results. Hence, the LMX2820 is powered up with the TPS62913 in this design and all AFE7950 performance results are with the TPS62913 on clocking board.

Figure 1-6 and Figure 1-7 show the phase noise and jitter performance of the LMX2820 at 9-GHz operating frequency with TPS62913 and TPS7A5301.

GUID-20211018-SS0I-DMTX-QD6D-R61FXHN0N1JC-low.png Figure 1-6 LMX2820 Phase Noise With TPS7A5A01
GUID-20211018-SS0I-B3TX-QQVW-2K2XRFLHRKTP-low.png Figure 1-7 LMX2820 Phase Noise With TPS62913